AM3892 datasheet(277/299 Pages) TI

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SPI_SCS[x] (Out)

SPI_SCLK (Out)

SPI_D[x] (In)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

SPI_SCS[x] (Out)

SPI_SCLK (Out)

SPI_D[x] (In)

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=1

EPOL=1

POL=0

POL=1

AM3894

AM3892

www.ti.com

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

Figure 8-85. SPI Master Mode Receive Timing

Table 8-100. Timing Requirements for SPI - Slave Mode

(see Figure 8-86 and Figure 8-87)

NO.

MIN

MAX

UNIT

tc(SPICLK)

Cycle time, SPI_CLK(1)(2)

62.5(3)

tw(SPICLKL)

Pulse duration, SPI_CLK low(1)

0.5*P - 3(4)

tw(SPICLKH)

Pulse duration, SPI_CLK high(1)

0.5*P - 3(4)

tsu(MOSI-SPICLK)

Setup time, SPI_D[x] valid before SPI_CLK active edge(1)

12.92

th(SPICLK-MOSI)

Hold time, SPI_D[x] valid after SPI_CLK active edge(1)

12.92

td(SPICLK-MISO)

Delay time, SPI_CLK active edge to SPI_D[x] transition(1)

-4.00

17.1

Delay time, SPI_SCS[x] active edge to SPI_D[x]

td(SCS-MISO)

17.1

transition(5)

tsu(SCS-SPICLK)

Setup time, SPI_SCS[x] valid before SPI_CLK first edge(1)

12.92

th(SPICLK-SCS)

Hold time, SPI_SCS[x] valid after SPI_CLK last edge(1)

12.92

(1)

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2)

Related to the input maximum frequency supported by the SPI module.

(3)

Maximum frequency = 16 MHz

(4)

P = SPICLK period.

(5)

PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

Peripheral Information and Timings

277

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