AM3892 datasheet(280/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.19 Timers

The device has seven 32-bit general-purpose (GP) timers that have the following features:

•

Timers 1-3 are for software use and do not have an external connection

•

Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)

signal

•

Interrupts generated on overflow, compare, and capture

•

Free-running 32-bit upward counter

•

Supported modes:

–

Compare and capture modes

–

Auto-reload mode

–

Start-stop mode

•

Timer[7:1] functional clock is sourced from either the 27-MHz system clock, 32.768-kHz RTC clock or

the TCLKIN external timer input clock, as selected within the PRCM

•

On-the-fly read/write register (while counting)

•

Generates interrupts to the ARM CPUs.

The device has one system watchdog timer that has the following features:

•

Free-running 32-bit upward counter

•

On-the-fly read/write register (while counting)

•

Reset upon occurrence of a timer overflow condition

•

Two possible clock sources:

–

Internal 32.768-kHz clock derived from 27-MHz system clock.

–

External clock input on the CLKIN32 input pin.

The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault

condition, such as a non-exiting code loop.

For more detailed information, see the Timers chapter in the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7).

8.19.1 Timer Peripheral Register Descriptions

Table 8-101. Timer1-7 Registers(1)

TIMER1 HEX

TIMER2 HEX

TIMER3 HEX

TIMER4 HEX

TIMER5 HEX

TIMER6 HEX

TIMER7 HEX

ACRONYM

ADDRESS

0x4802 E000

0x4804 0000

0x4804 2000

0x4804 4000

0x4804 6000

0x4804 8000

0x4804 A000

TIDR

Identification

0x4802 E010

0x4804 0010

0x4804 2010

0x4804 4010

0x4804 6010

0x4804 8010

0x4804 A010

TIOCP_CFG

Timer OCP

Configuration

0x4802 E020

0x4804 0020

0x4804 2020

0x4804 4020

0x4804 6020

0x4804 8020

0x4804 A020

IRQ_EOI

Timer IRQ

End-Of-Interrupt

0x4802 E024

0x4804 0024

0x4804 2024

0x4804 4024

0x4804 6024

0x4804 8024

0x4804 A024

IRQSTATUS_

Timer IRQSTATUS

RAW

Raw

0x4802 E028

0x4804 0028

0x4804 2028

0x4804 4028

0x4804 6028

0x4804 8028

0x4804 A028

IRQSTATUS

Timer IRQSTATUS

0x4802 E02C

0x4804 002C

0x4804 202C

0x4804 402C

0x4804 602C

0x4804 802C

0x4804 A02C

IRQSTATUS_

Timer IRQENABLE

SET

Set

0x4802 E030

0x4804 0030

0x4804 2030

0x4804 4030

0x4804 6030

0x4804 8030

0x4804 A030

IRQSTATUS_

Timer IRQENABLE

CLR

Clear

0x4802 E034

0x4804 0034

0x4804 2034

0x4804 4034

0x4804 6034

0x4804 8034

0x4804 A034

IRQWAKEEN

Timer IRQ Wakeup

Enable

0x4802 E038

0x4804 0038

0x4804 2038

0x4804 4038

0x4804 6038

0x4804 8038

0x4804 A038

TCLR

Timer Control

0x4802 E03C

0x4804 003C

0x4804 203C

0x4804 403C

0x4804 603C

0x4804 803C

0x4804 A03C

TCRR

Timer Counter

0x4802 E040

0x4804 0040

0x4804 2040

0x4804 4040

0x4804 6040

0x4804 8040

0x4804 A040

TLDR

Timer Load

0x4802 E044

0x4804 0044

0x4804 2044

0x4804 4044

0x4804 6044

0x4804 8044

0x4804 A044

TTGR

Timer Trigger

(1)

All Timer registers are: 32-bit register accessible in 16-bit mode and use little-endian addressing.

280

Peripheral Information and Timings

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