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AM3892 Datasheet(PDF) 284 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 284 Page - Texas Instruments |
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284 / 299 page  AM3894 AM3892 SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 www.ti.com 8.20.1 UART Peripheral Register Descriptions Table 8-105 lists the UART register name summary. Table 8-106 shows the UART registers along with their configuration requirements. Table 8-105. UART Register Summary ACRONYM REGISTER NAME ACRONYM REGISTER NAME RHR Receive Holding RXFLH Receive Frame Length High THR Transmit Holding BLR BOF Control IER Interrupt Enable ACREG Auxilliary Control IIR Interrupt Identification SCR Supplementary Control FCR FIFO Control SSR Supplementary Status LCR Line Control EBLR BOF Length MCR Modem Control MVR Module Version LSR Line Status SYSC System Configuration MSR Modem Status SYSS System Status SPR Scratchpad WER Wake-up Enable TCR Transmission Control CFPS Carrier Frequency Prescaler TLR Trigger Level DLL Divisor Latch Low MDR1 Mode Definition 1 DLH Divisor Latch High MDR2 Mode Definition 2 UASR UART Autobauding Status SFLSR Status FIFO Line Status EFR Enhanced Feature RESUME Resume XON1 UART XON1 Character SFREGL Status FIFO Low XON2 UART XON2 Character SFREGH Status FIFO High XOFF1 UART XOFF1 Character TXFLL Transmit Frame Length Low XOFF2 UART XOFF2 Character TXFLH Transmit Frame Length High ADDR1 IrDA Address 1 RXFLL Receive Frame Length Low ADDR2 IrDA Address 2 Table 8-106. UART Registers Configuration Requirements(1)(2)(3) REGISTER UART0 HEX UART1 HEX UART2 HEX LCR[7] = 1 and LCR[7:0] LCR[7] = 0 LCR[7:0] = 0xBF ADDRESS ADDRESS ADDRESS ≠ 0xBF READ WRITE READ WRITE READ WRITE 0x4802 0000 0x4802 2000 0x4802 4000 RHR THR DLL DLL DLL DLL 0x4802 0004 0x4802 2004 0x4802 4004 IER IER DLH DLH DLH DLH 0x4802 0008 0x4802 2008 0x4802 4008 IIR FCR IIR FCR EFR EFR 0x4802 000C 0x4802 200C 0x4802 400C LCR LCR LCR LCR LCR LCR 0x4802 0010 0x4802 2010 0x4802 4010 MCR MCR MCR MCR XON1/ XON1/ ADDR1 ADDR1 0x4802 0014 0x4802 2014 0x4802 4014 LSR - LSR - XON2/ XON2/ ADDR2 ADDR2 0x4802 0018 0x4802 2018 0x4802 4018 MSR/TCR TCR MSR/TCR TCR XOFF1/ XOFF1/ TCR TCR 0x4802 001C 0x4802 201C 0x4802 401C SPR/TLR SPR/TLR SPR/TLR SPR/TLR XOFF2/ XOFF2/ TLR TLR 0x4802 0020 0x4802 2020 0x4802 4020 MDR1 MDR1 MDR1 MDR1 MDR1 MDR1 0x4802 0024 0x4802 2024 0x4802 4024 MDR2 MDR2 MDR2 MDR2 MDR2 MDR2 0x4802 0028 0x4802 2028 0x4802 4028 SFLSR TXFLL SFLSR TXFLL SFLSR TXFLL (1) The transmission control register (TCR) and the trigger level register (TLR) are accessible only when EFR[4]=1 and MCR[6]=1. (2) MCR[7:5] and FCR[5:4] can only be written when EFR[4]=1. (3) In UART modes, IER[7:4] can only be written when EFR[4]=1. In IrDA/CIR modes, EFR[4] has no impact on the access to IER[7:4]. 284 Peripheral Information and Timings Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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