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OR4E2 Datasheet(PDF) 89 Page - Agere Systems |
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OR4E2 Datasheet(HTML) 89 Page - Agere Systems |
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89 / 124 page  Lucent Technologies Inc. 89 Preliminary Data Sheet December 2000 ORCA Series 4 FPGAs Pin Information (continued) As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows: s _A1 indicates one ball between pairs. s _A2 indicates two balls between pairs. s _D0 indicates balls are diagonally adjacent. s _D1 indicates diagonally adjacent separated by one physical ball. VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank). Table 45. 432-Pin EBGA 432 BGA Ball VDDIO Bank VREF Group General-Purpose User I/O Additional Function Pair Differential OR4E2 OR4E4 OR4E6 B19 0 1 PT11D PT13D PT18D MPI_RTRY L1C_A0 COMPLEMENT C19 0 1 PT11C PT13C PT18C MPI_ACK L1T_A0 TRUE D19 0 1 PT11B PT13B PT17D — L2C_D0 COMPLEMENT C20 0 1 PT11A PT13A PT17C VREF_TL_01 L2T_D0 TRUE A21 0 1 PT10D PT12D PT16D M0 L3C_A0 COMPLEMENT B21 0 1 PT10C PT12C PT16C M1 L3T_A0 TRUE A22 0 2 PT9D PT11D PT14D M2 L5C_A0 COMPLEMENT B22 0 2 PT9C PT11C PT14C M3 L5T_A0 TRUE C22 0 2 PT9B PT11B PT13D VREF_TL_02 L6C_D1 COMPLEMENT A23 0 2 PT9A PT11A PT13C MPI_TEA L6T_D1 TRUE D20 0 2 PT10B PT12B PT15D MPI_CLK L4C_D0 COMPLEMENT C21 0 2 PT10A PT12A PT15C A21/MPI_BURST L4T_D0 TRUE B23 0 3 PT8B PT9D PT11D VREF_TL_03 L7C_D1 COMPLEMENT D22 0 3 PT8A PT9C PT11C — L7T_D1 TRUE C23 0 3 PT7D PT8D PT10D D0 L8C_D0 COMPLEMENT B24 0 3 PT7C PT8C PT10C TMS L8T_D0 TRUE C24 0 4 PT7B PT7D PT9D A20/MPI_BDIP L9C_D0 COMPLEMENT D23 0 4 PT7A PT7C PT9C A19/MPI_TSZ1 L9T_D0 TRUE A25 0 4 PT6D PT6D PT8D A18/MPI_TSZ0 L10C_A0 COMPLEMENT B25 0 4 PT6C PT6C PT8C D3 L10T_A0 TRUE D24 0 5 PT5D PT5D PT6D D1 L11C_D2 COMPLEMENT A26 0 5 PT5C PT5C PT6C D2 L11T_D2 TRUE B26 0 5 PT4D PT4D PT4D TDI L12C_A0 COMPLEMENT C26 0 5 PT4C PT4C PT4C TCK L12T_A0 TRUE A27 0 6 PT3D PT3D PT3D — L13C_A0 COMPLEMENT B27 0 6 PT3C PT3C PT3C VREF_TL_06 L13T_A0 TRUE C27 0 6 PT2D PT2D PT2D PLL_CK1C L14C_D0 COMPLEMENT D26 0 6 PT2C PT2C PT2C PLL_CK1T L14T_D0 TRUE F31 0 7 PL3D PL4D PL4D D5 L17C_D2 COMPLEMENT H28 0 7 PL3C PL4C PL4C D6 L17T_D2 TRUE E30 0 7 PL2D PL2D PL2D PLL_CK0C L15C_A0 COMPLEMENT E31 0 7 PL2C PL2C PL2C PLL_CK0T L15T_A0 TRUE |
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