OR4E2 datasheet(67/124 Pages) AGERE

67 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes (continued)

5-5761(F)

Figure 41. PowerPC/MPI Configuration Schematic

Configuration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user

mode by setting the MPI_USER_ENABLE bit to 1 in the configuration control register prior to the start of configura-

tion or through a configuration option. To perform readback, the host processor writes the 14-bit readback start

address to the readback address registers and sets the RD_CFG bit to 0 in the configuration control register. Read-

back data is returned 8 bits at a time to the readback data register and is valid when the DATA_RDY bit of the status

Figure 43. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI readback.

DOUT

CCLK

D[#:0]

A[17:0]

MPI_CLK

MPI_RW

MPI_ACK

MPI_BDIP

MPI_IRQ

MPI_STRB

CS0

CS1

HDC

LDC

D[#:0]

A[14:31]

CLKOUT

RD/WR

BDIP

IRQx

TO DAISY-

CHAINED

DEVICES

POWERPC

ORCA

8, 16, 32

FPGA

SERIES 4

DONE

INIT

BUS

CONTROLLER

OR4E2 Datasheet(PDF) 67 Page - Agere Systems

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