OR4E2 datasheet(34/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

Inputs

There are many major options on the PIO inputs that

can be selected in the ORCA Foundry tools listed in

Table 15. Inputs may have a pull-up or pull-down resis-

tor selected on an input for signal stabilization and

power management. A weak keeper circuit is also

available on inputs. Input signals in a PIO are passed to

CIB routing and/or a fast route into the clock routing

system.

There is also a programmable delay available on the

input. When enabled, this delay affects the INFF and

INDD signals of each PIO, but not the clock input. The

delay allows any signal to have a guaranteed zero hold

time when input. This feature is discussed subse-

quently.

Inputs should have transition times of less than 500 ns

and should not be left floating. If any pin is not used, it

is 3-stated with an internal pull-up resistor enabled

automatically after configuration.

Floating inputs increase power consumption, produce

oscillations, and increase system noise. The inputs

have a typical hysteresis of approximately 250 mV to

reduce sensitivity to input noise. The PIC contains

input circuitry that provides protection against latch-up

and electrostatic discharge.

The other features of the PIO inputs relate to the latch/

FF structure in the input path. In latch mode, the input

signal is fed to a latch that is clocked by either the pri-

mary, secondary, or edge clock signal. The clock may

be inverted or noninverted. There is also a local set/

reset signal to the latch. The senses of these signals

are also programmable and have the capability to

enable or disable the global set/reset signal and select

the set/reset priority. The same control signals may

also be used to control the input latch/FF when it is

configured as a FF instead of a latch, with the addition

of another control signal used as a clock enable. The

PIOs are paired together and have independent CE,

set/reset, and GSRN control signals for the pair. Note

that these control signals are paired to the same pair of

pins used for differential signaling.

The input path is also capable of accepting data from

any pad using a fast capture feature. This feature can

be programmed as a latch or FF referenced to any

clock. There are two options for zero-hold input capture

in the PIO. If input delay mode is selected to delay the

signal from the input pin, data can be either registered

or latched with guaranteed zero-hold time in the PIO

using a system clock. To further improve setup time,

the fast zero-hold mode of the PIO input takes advan-

tage of the latch/FF combination and sources the input

FF data from a dedicated latch that is clocked by a fast

edge clock

from the dedicated clock pads or any local

pad. The input FF is then driven by a primary clock

sourced from a dedicated input pin designed for fast,

low-skew operation at the I/Os. These dedicated pads

are located in pairs in the center of each side of the

array and if not utilized by the clock spine can be used

as general user I/O. The clock inputs to both the dedi-

cated fast capture latch and the input FF can also be

driven by the on-chip PLLs.

The combination of input register capability provides for

input signal demultiplexing without any additional

resources such as for address and data arriving on the

same pins. On the positive edge of the clock, the data

would come from the pad to latch. The PIO input signal

is sent to both the input latch and directly to INDD. The

signal is latched on the falling edge of the clock and

output to routing at INFF. The address and data are

then both available at the rising edge of the clock.

These signals may be registered or otherwise pro-

cessed in the PLCs.

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