OR4E2 datasheet(32/124 Pages) AGERE

32 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

On the output side of each PIO, an output from the PLC

array can be routed to each output FF, and logic can be

associated with each I/O pad. The output logic associ-

ated with each pad allows for multiplexing of output sig-

nals and other functions of two output signals.

The output FF, in combination with output signal multi-

plexing, is particularly useful for registering address

signals to be multiplexed with data, allowing a full clock

cycle for the data to propagate to the output. The out-

put buffer signal can be inverted, and the 3-state con-

trol can be made active-high, active-low, or always

enabled. In addition, this 3-state signal can be regis-

tered or nonregistered.

The Series 4 I/O logic has been enhanced to include

modes for speed uplink and downlink capabilities.

These modes are supported through shift register logic

which divides down incoming data rates or multiplies

up outgoing data rates. This new logic block also sup-

ports high-speed DDR mode requirements where data

is clocked into and out of the I/O buffers on both edges

of the clock.

The new programmable I/O cell allows designers to

select I/Os that meet many new communication stan-

dards permitting the device to hook up directly without

any external interface translation. They support tradi-

tional FPGA standards as well as high-speed single-

ended and differential pair signaling (as shown in

Table 14). Based on a programmable, bank-oriented

I/O ring architecture, designs can be implemented

using 3.3 V, 2.5 V, 1.8 V, and 1.5 V output levels.

Table 14. Series 4 Programmable I/O Standards

Note: Interfaces to DDR and ZBT memories are supported through the interface standards shown above.

Standard

VDDIO (V) VREF (V)

Interface Usage

LVTTL

3.3

General purpose.

LVCMOS2

2.5

LVCMOS1.8

1.8

PCI

3.3

PCI.

LVDS

2.5

Point to point and multidrop backplanes, high noise immunity.

Bused-LVDS

2.5

Network backplanes, high noise immunity, bus architecture

backplanes.

LVPECL

2.5

Network backplanes, differential 100 MHz+ clocking, optical

transceiver, high-speed networking.

PECL

3.3

2.0

Backplanes.

GTL

3.3

0.8

Backplane or processor interface.

GTL+

3.3

1.0

HSTL-Class I

1.5

0.75

High-speed SRAM and networking interfaces.

HTSL-Class III and IV

1.5

0.9

STTL3-Class I and II

3.3

1.5

Synchronous DRAM interface.

SSTL2-Class I and II

2.5

1.25

OR4E2 Datasheet(PDF) 32 Page - Agere Systems

OR4E2 Datasheet(HTML) 32 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL