OR4E2 datasheet(64/124 Pages) AGERE

64 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes (continued)

In master parallel mode, the starting memory address

is 00000 hex, and the FPGA increments the address

for each byte loaded.

One master mode FPGA can interface to the memory

and provide configuration data on DOUT to additional

FPGAs in a daisy-chain. The configuration data on

DOUT is provided synchronously with the falling edge

of CCLK. The frequency of the CCLK output is eight

times that of RCLK.

Master Serial Mode

In the master serial mode, the FPGA loads the configu-

ration data from an external serial ROM. The configura-

tion data is either loaded automatically at start-up or on

a PRGM command to reconfigure. Serial PROMs can

be used to configure the FPGA in the master serial

mode.

Configuration in the master serial mode can be done at

powerup and/or upon a configure command. The sys-

tem or the FPGA must activate the serial ROM's

RESET

/OE and CE inputs. At powerup, the FPGA and

serial ROM each contain internal power-on reset cir-

cuitry that allows the FPGA to be configured without

the system providing an external signal. The power-on

reset circuitry causes the serial ROM's internal address

pointer to be reset. After powerup, the FPGA automati-

cally enters its initialization phase.

The serial ROM/FPGA interface used depends on such

factors as the availability of a system reset pulse, avail-

ability of an intelligent host to generate a configure

command, whether a single serial ROM is used or mul-

tiple serial ROMs are cascaded, whether the serial

ROM contains a single or multiple configuration pro-

grams, etc. Because of differing system requirements

and capabilities, a single FPGA/serial ROM interface is

generally not appropriate for all applications.

Data is read in the FPGA sequentially from the serial

ROM. The DATA output from the serial ROM is con-

nected directly into the DIN input of the FPGA. The

CCLK output from the FPGA is connected to the CLK

input of the serial ROM. During the configuration pro-

cess, CCLK clocks one data bit on each rising edge.

Since the data and clock are direct connects, the

FPGA/serial ROM design task is to use the system or

FPGA to enable the RESET/OE and CE of the serial

ROM(s). There are several methods for enabling the

serial ROM’s RESET/OE and CE inputs. The serial

ROM’s RESET/OE is programmable to function with

RESET active-high and OE active-low or RESET active-

low and OE active-high.

In Figure 39, serial ROMs are cascaded to configure

multiple daisy-chained FPGAs. The host generates a

500 ns low pulse into the FPGA's PRGM input. The

FPGA’s INIT input is connected to the serial ROMs’

RESET

/OE input, which has been programmed to

function with RESET active-low and OE active-high.

The FPGA DONE is routed to the CE pin. The low on

DONE enables the serial ROMs. At the completion of

configuration, the high on the FPGA’s DONE disables

the serial ROM.

Serial ROMs can also be cascaded to support the con-

figuration of multiple FPGAs or to load a single FPGA

when configuration data requirements exceed the

capacity of a single serial ROM. After the last bit from

the first serial ROM is read, the serial ROM outputs

CEO

low and 3-states the DATA output. The next serial

ROM recognizes the low on CE input and outputs con-

figuration data on the DATA output. After configuration

is complete, the FPGA’s DONE output into CE disables

the serial ROMs.

This FPGA/serial ROM interface is not used in applica-

tions in which a serial ROM stores multiple configura-

tion programs. In these applications, the next

configuration program to be loaded is stored at the

ROM location that follows the last address for the previ-

ous configuration program. The reason the interface in

Figure 39 will not work in this application is that the low

output on the INIT signal would reset the serial ROM

address pointer, causing the first configuration to be

reloaded.

In some applications, there can be contention on the

FPGA's DIN pin. During configuration, DIN receives

configuration data, and after configuration, it is a user

I/O. If there is contention, an early DONE at start-up

(selected in ORCA Foundry) may correct the problem.

An alternative is to use LDC to drive the serial ROM's

pin. In order to reduce noise, it is generally better to

run the master serial configuration at 1.25 MHz (M3 pin

tied high), rather than 10 MHz, if possible.

OR4E2 Datasheet(PDF) 64 Page - Agere Systems

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