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OR4E2 Datasheet(PDF) 54 Page - Agere Systems

Part # OR4E2
Description  Field-Programmable Gate Arrays
PDF  124 Pages
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Manufacturer  AGERE [Agere Systems]
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OR4E2 Datasheet(HTML) 54 Page - Agere Systems

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54
Lucent Technologies Inc.
Preliminary Data Sheet
December 2000
ORCA Series 4 FPGAs
Phase-Locked Loops (continued)
Table 33. Dedicated Pin Per Package
Table 34. STS-3/STM-1 DPLL Specifications
0045(F)
Figure 32. PLL Naming Scheme
Dedicated PLL_VF Pin Per Package
BA352
BC432
BM680
B24
C4
D30
Parameter
Min
Nom
Max
Unit
Input Clock Frequency
—
155.52
—
MHz
Output Clock Frequency
—
155.52
—
MHz
Input Duty Cycle Tolerance
30
—
70
%
Output Duty Cycle
47
50
53
%
dc Power
—
50
—
mW
Total On Current
—
2.4
—
mA
Total Off Current
—
30
—
pA
Cycle to Cycle Jitter (p-p)
0.02
UIp-p
Lock Time
—
<50
—
µs
LRPPLL
LRPLL2
LLPPLL LLHPPLL
URPPLL URPLL1
ULPPLL ULHPPLL



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