OR4E2 datasheet(48/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Microprocessor Interface (MPI)

The Series 4 FPGAs have a dedicated synchronous MPI function block. The MPI is programmable to operate with

PowerPC MPC860/MPC8260 series microprocessors. The pin listing is shown in Table 26. The MPI implements an

8-, 16-, or 32-bit interface with 4-bit parity to the host processor (PowerPC) that can be used for configuration and

readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In

addition to dedicated-function registers, the MPI bridges to the AMBA embedded system bus through which the

PowerPC bus master can access the FPGA configuration logic, EBR, and other user logic. There is also capability

to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the

embedded system bus.

The control portion of the MPI is available following powerup of the FPGA if the mode pins specify MPI mode, even

if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus

can be 1-, 2-, or 4- bit. In configuration mode, the data bus width and parity are related to the state of the M[0:3]

mode pins. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI

library element in your design from the ORCA macro library, or by setting the bit of the MPI configuration control

ration bit stream. These pads can be used as general I/O when they are not needed for MPI use.

The ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The MPI interfaces to the user-pro-

grammable FPGA logic using the AMBA embedded system bus. The MPI has access to a series of addressable

registers made accessible by the AMBA system bus that provide FPGA control and status, configuration and read-

back data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits

wide. The address map for these registers and the user-logic address space utilize the same registers as the

AMBA embedded system bus. The internal AMBA bus is 32 bits wide and the proper transformation of 8-, 16-, or

32-bit data of the MPI is done when transferring data between the MPI and ESB.

Table 26. MPC 860 to ORCA MPI Interconnection

PowerPC

Signal

ORCA Pin

Name

MPI

I/O

Function

D[n:0]

D[31:0]

I/O

8-, 16-, 32-bit data bus.

DP[m:0]

DP[3:0]

I/O

Selectable parity bus width from 1-, 2-, and 4-bit.

A[14:31]

A[17:0]

32-bit MPI address bus.

MPI_STRB

Transfer start signal.

BURST

MPI_BURST

Active-low indicates burst transfer in-progress/high indicates current transfer

not a burst.

—

CS0

Active-low MPI select.

—

CS1

Active-high MPI select.

CLKOUT

MPI_CLK

PowerPC interface clock.

RD/WR

MPI_RW

Read (high)/write (low) signal.

MPI_ACK

Active-low transfer acknowledge signal.

BDIP

MPI_BDIP

Active-low burst transfer in progress signal indicates that the second beat in

front of the current one is requested by the master. Negated before the burst

transfer ends to abort the burst data phase.

Any of

IRQ[7:0]

MPI_IRQ

Active-low interrupt request signal.

TEA

MPI_TEA

Active-low indicates MPI detects a bus error on the internal system bus for

current transaction.

RETRY

MPI_RTRY

Requests the MPC860 to relinquish the bus and retry the cycle.

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