OR4E2 datasheet(29/124 Pages) AGERE

29 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded Block RAM (continued)

0308 (F)

Figure 21. EBR Read and Write Cycles with Write Through

Table 10. FIFO Signals

Port Signals

I/O

Function

AR(1:0)[9:0]

Programs FIFO flags. Used for partially empty flag size.

AW(1:0)[9:0]

Programs FIFO flags. Used for partially full flag size.

Full flag.

PFF

Partially full flag.

PEF

Partially empty flag.

Empty flag.

D0[17:0]

Data inputs for all configurations.

D1[17:0]

Data inputs for 256 x 36 configurations only.

CKW[0:1]

Positive-edge write port clock. Port 1 only used for 256 x 36 configurations.

CKR[0:1]

Positive-edge read port clock. Port 1 only used for 256 x 36 configurations.

CSW[1:0]

Active-high write enable. Port 1 only used for 256 x 36 configurations.

CSR[1:0]

Active-high read enable. Port 1 only used for 256 x 36 configurations.

RESET

Active-low. Resets FIFO pointers.

Q0[17:0]

Data outputs for all configurations.

Q1[17:0]

Data outputs for 256 x 36 configurations.

CKWPH

CKWPL

CSWSU

CSWH

AWH

DSU

BWSU

BWH

AWSU

CKWQ

AQH

CKW

CSW

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