OR4E2 datasheet(43/124 Pages) AGERE

43 / 124 page

Preliminary Data Sheet

December 2000

Lucent Technologies Inc.

ORCA Series 4 FPGAs

Special Function Blocks (continued)

5-5768(F)

Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram

TAP

CONTROLLER

TMS

TCK

BOUNDARY-SCAN REGISTER

USER CODE REGISTERS

BYPASS REGISTER

DATA

MUX

INSTRUCTION DECODER

INSTRUCTION REGISTER

RESET

CLOCK IR

SHIFT-IR

UPDATE-IR

PUR

TDO

SELECT

ENABLE

RESET

CLOCK DR

SHIFT-DR

UPDATE-DR

TDI

DATA REGISTERS

PSR1/PSR2/PSR3 REGISTERS (PLCs)

CONFIGURATION REGISTER

(RAM_R, RAM_W)

PRGM

I/O BUFFERS

VDD

IDCODE REGISTER

ORCA Series TAP Controller

The ORCA Series TAP controller is a 1149 compatible

TAPC. The 16 JTAG state assignments from the IEEE

1149 specification are used. The TAPC is controlled by

TCK and TMS. The TAPC states are used for loading

the IR to allow three basic functions in testing: provid-

ing test stimuli (Update-DR), providing test execution

(Run-Test/Idle), and obtaining test responses (Capture-

DR). The TAPC allows the test host to shift in and out

both instructions and test data/results. The inputs and

outputs of the TAPC are provided in the table below.

The outputs are primarily the control signals to the

instruction register and the data register.

Table 24. TAP Controller Input/Outputs

Symbol

I/O

Function

TMS

Test Mode Select

TCK

Test Clock

PUR

Powerup Reset

PRGM

IBSCAN Reset

TRESET

Test Logic Reset

Select

Select IR (High); Select-DR (Low)

Enable

Test Data Out Enable

Capture-DR

Capture/Parallel Load-DR

Capture-IR

Capture/Parallel Load-IR

Shift-DR

Shift Data Register

Shift-IR

Shift Instruction Register

Update-DR

Update/Parallel Load-DR

Update-IR

Update/Parallel Load-IR

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