OR4E2 datasheet(72/124 Pages) AGERE

72 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes (continued)

5-4488(F

Figure 46. Daisy-Chain Configuration Schematic

VDD

EPROM

PROGRAM

D[7:0]

A[17:0]

D[7:0]

DONE

HDC

LDC

RCLK

CCLK

DOUT

DIN

DOUT

DIN

CCLK

DONE

DOUT

INIT

CCLK

VDD

VDD OR

GND

PRGM

VDD

HDC

LDC

RCLK

HDC

LDC

RCLK

VDD

ORCA

SERIES

FPGA

SLAVE 2

ORCA

SERIES

FPGA

MASTER

ORCA

SERIES

FPGA

SLAVE 1

As seen in Figure 46, the INIT pins for all of the FPGAs

are connected together. This is required to guarantee

that powerup and initialization will work correctly. In

general, the DONE pins for all of the FPGAs are also

connected together as shown to guarantee that all of

the FPGAs enter the start-up state simultaneously. This

may not be required, depending upon the start-up

sequence desired.

Daisy-Chaining with Boundary Scan

Multiple FPGAs can be configured through the JTAG

ports by using a daisy chain of the FPGAs. This daisy-

chaining operation is available upon initial configuration

after powerup, after a power-on reset, after pulling the

program pin to reset the chip, or during a reconfigura-

tion if the EN_JTAG RAM has been set.

All daisy-chained FPGAs are connected in series.

Each FPGA reads and shifts the preamble and length

count in on the positive TCK and out on the negative

TCK edges.

An upstream FPGA that has received the preamble

and length count outputs a high on TDO until it has

received the appropriate number of data frames so that

downstream FPGAs do not receive frame start bit

pairs. After loading and retransmitting the preamble

and length count to a daisy chain of downstream

devices, the lead device loads its configuration data

frames.

The loading of configuration data continues after the

lead device had received its configuration read into TDI

of downstream devices on the positive edge of TCK,

and shifted out TDO on the negative edge of TCK.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings

can cause permanent damage to the device. These are

absolute stress ratings only. Functional operation of the

device is not implied at these or any other conditions in

excess of those given in the operations sections of this

data sheet. Exposure to absolute maximum ratings for

extended periods can adversely affect device reliability.

The ORCA Series FPGAs include circuitry designed to

protect the chips from damaging substrate injection

currents and to prevent accumulations of static charge.

Nevertheless, conventional precautions should be

observed during storage, handling, and use to avoid

exposure to excessive electrical stress.

OR4E2 Datasheet(PDF) 72 Page - Agere Systems

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