OR4E2 datasheet(52/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Phase-Locked Loops

There are eight PLLs available to perform many clock

modification and clock conditioning functions on the

Series 4 FPGAs. Six of the PLLs are programmable

allowing the user the flexibility to configure the PLL to

manipulate the frequency, phase, and duty cycle of a

clock signal. Four of the programmable PLLs are capa-

ble of manipulating and conditioning clocks from

20 MHz to 200 MHz and two others are capable of

manipulating and conditioning clocks from 60 MHz to

420 MHz. Frequencies can be adjusted from 1/8x to 8x

the input clock frequency. Each programmable PLL

provides two outputs that have different multiplication

factors with the same phase relationships. Duty cycles

and phase delays can be adjusted in 12.5% of the

clock period increments. An input buffer delay compen-

sation mode is available for phase delay. Each PPLL

provides two outputs (MCLK, NCLK) that can have pro-

grammable (12.5% steps) phase differences.

The PPLLs can be utilized to eliminate skew between

the clock input pad and the internal clock inputs across

the entire device. The PPLLs can drive onto the pri-

mary, secondary, and edge clock networks inside the

FPGA. Each PPLL can take a clock input from the ded-

icated pad or differential pair of pads in its corner or

from general routing resources.

Functionality of the PPLLs is programmed during oper-

ation through a read/write interface to the internal sys-

tem bus command and status registers or via the

configuration bit stream. There is also a PLL output sig-

nal, LOCK, that indicates a stable output clock state.

Unlike Series 3, this signal does not have to be inter-

grated before use.

Table 31. PPLL Specifications

Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system

designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to target

very tightly specified clock conditioning not available in the universal PPLLs. DPLLs are targeted to low-speed net-

working DS1 and E1 and high-speed SONET/SDH networking STS-3 and STM-1 systems.

Parameter

Min

Nom

Max

Unit

VDD1.5

1.425

1.5

1.575

VDD3.3

3.0

3.3

3.6

Operating Temp

–40

125

°C

Input Clock Voltage

1.425

1.5

1.575

Output Clock Voltage

1.425

1.5

1.575

Input Clock Frequency

(no division)

PPLL

—

200

MHz

HPPLL

—

420

Output Clock Frequency

PPLL

—

200

MHz

HPPLL

—

420

Input Duty Cycle Tolerance

—

Output Duty Cycle

dc Power

—

Total On Current

—

8.5

—

Total Off Current

—

Cycle to Cycle Jitter (p-p)

—

<0.02

—

UIp-p

Lock Time

—

<50

—

µs

Frequency Multiplication

1x, 2x, 3x, 4x, 5x, 6x, 7x, 8x,

—

Frequency Division

1/8, 1/7, 1/6, 1/5, 1/4, 1/3, 1/2

—

Duty Cycle Adjust of Output Clock

12.5, 25, 37.5, 50, 62.5, 75, 87.5

Delay Adjust of Output Clock

0, 12.5, 25, 37.5, 50, 62.5, 75, 87.5

Phase Shift Between MCLK & NCLK

0, 45, 90, 135, 180, 225, 270, 315

degree

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