OR4E2 datasheet(75/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Pin Information

Pin Descriptions

This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-

mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.

If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled

after configuration.

Table 42. Pin Descriptions

Symbol

I/O

Description

Dedicated Pins

VDD33

— 3 V positive power supply.

VDD15

— 1.5 V positive power supply for internal logic.

VDDIO

— Positive power supply used by I/O banks.

GND

— Ground supply.

PLL_VF

— Dedicated pins for PLL filtering.

PTEMP

Temperature-sensing diode pin. Dedicated input.

RESET

During configuration, RESET forces the restart of configuration and a pull-up is enabled.

After configuration, RESET can be used as a general FPGA input or as a direct input,

which causes all PLC latches/FFs to be asynchronously set/reset.

CCLK

In the master and asynchronous peripheral modes, CCLK is an output which strobes con-

figuration data in. In the slave or readback after configuration, CCLK is input synchronous

with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead

device is in master, peripheral, or system bus modes.

DONE

As an input, a low level on DONE delays FPGA start-up after configuration.*

As an active-high, open-drain output, a high level on this signal indicates that configura-

tion is complete. DONE has an optional pull-up resistor.

PRGM

is an active-low input that forces the restart of configuration and resets the bound-

ary-scan circuitry. This pin always has an active pull-up.

RD_CFG

This pin must be held high during device initialization until the INIT pin goes high. This pin

always has an active pull-up.

During configuration, RD_CFG is an active-low input that activates the TS_ALL function

and 3-states all of the I/O.

After configuration, RD_CFG can be selected (via a bit stream option) to activate the

TS_ALL function as described above, or, if readback is enabled via a bit stream option, a

high-to-low transition on RD_CFG will initiate readback of the configuration data, including

PFU output states, starting with frame address 0.

RD_DATA/TDO

RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configura-

tion data out. If used in boundary-scan, TDO is test data out.

CFG_IRQ/MPI_IRQ

During JTAG, slave, master, and asynchronous peripheral configuration assertion by the

FPGA on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC ini-

tialization.

MPI

active-low interrupt request output.

* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all

user I/Os) is controlled by a second set of options.

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