OR4E2 datasheet(30/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded Block RAM (continued)

Table 11. Constant Multiplier Signals

Table 12. 8 x 8 Multiplier Signals

Table 13. CAM Signals

Port Signals

I/O

Function

AR0[15:0]

Data input—operand.

AW(1:0)[8:0]

Address bits.

D(1:0)[17:0]

Data inputs to load memory or change coefficient.

CKW[0:1]

Positive-edge write port clock.

CKR[0:1]

Positive-edge read port clock. Used for synchronous multiply mode.

CSW[1:0]

Active-high write enable.

CSR[1:0]

Active-high read enable.

Q[23:0]

Data outputs—product result.

Port Signals

I/O

Function

AR0[7:0]

Data input—multiplicand.

AR1[7:0]

Data input—multiplier.

AW(1:0)[8:0]

Address bits for memory.

D(1:0)[17:0]

Data inputs to load memory.

CKW[0:1]

Positive-edge write port clock.

CKR[0:1]

Positive-edge read port clock. Used for synchronous multiply mode.

CSW[1:0]

Active-high write enable.

CSR[1:0]

Active-high enables. For enabling address registers.

BW(1:0)[1:0]

Byte-lane write for loading memory.

Q[15:0]

Data outputs—product.

Port Signals

I/O

Function

AR(1:0)[7:0]

Data match.

AW(1:0)[8:0]

Data write.

D(1:0)[17]

Clear data active-high.

D(1:0)[16]

Single match active-high.

D(1:0)[3:0]

CAM address for data write.

CSW[1:0]

Active-high write enable. Enable for CAM data write.

CSR[1:0]

Active-high enable data registers. Enable for CAM data registers.

Q(1:0)15:0]

Decoded data outputs. 1 corresponds to a data match at that address location.

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