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OR4E2 Datasheet(PDF) 50 Page - Agere Systems |
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OR4E2 Datasheet(HTML) 50 Page - Agere Systems |
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50 / 124 page  50 Lucent Technologies Inc. Preliminary Data Sheet December 2000 ORCA Series 4 FPGAs Embedded System Bus (ESB) (continued) Table 27. Embedded System Bus/MPI Registers Table 28. Interrupt Register Space Assignments Register Byte Read/Write Initial Value Description 00 03—00 RO — 32-bit device ID 01 07—04 R/W — Scratchpad register 02 0B—08 R/W — Command register 03 0F—0C RO — Status register 04 13 R/W — Interrupt enable register—MPI 12 R/W — Interrupt enable register—USER 11 R/W — Interrupt enable register—FPSC 10 RO — Interrupt cause register 05 17—14 R/W — Readback address register (14 bits) 06 1B—18 RO — Readback data register 07 1F—1C R/W — Configuration data register 08 23—20 RO — Reserved 09 27—24 RO — Bus error address register 0A 2B—28 RO — Interrupt vector 1 predefined by configuration bit stream 0B 2F—2C RO — Interrupt vector 2 predefined by configuration bit stream 0C 33—30 RO — Interrupt vector 3 predefined by configuration bit stream 0D 37—34 RO — Interrupt vector 4 predefined by configuration bit stream 0E 3B—38 RO — Interrupt vector 5 predefined by configuration bit stream 0F 3F—3C RO — Interrupt vector 6 predefined by configuration bit stream 10 43—40 —— Top-left PPLL control/status 11 47—44 —— Top-left HPLL control/status 14 53—50 —— Top-right PPLL control/status 18 63—60 —— Bottom-left PPLL control/status 19 67—64 —— Bottom-left HPLL control/status 1C 73—70 —— Bottom-right PPLL control/status Byte Bit Read/Write Description 13 7—0 R/W Interrupt enable register—MPI 12 7—0 R/W Interrupt enable register—USER 11 7—0 R/W Interrupt enable register—FPSC 10 Interrupt cause registers 7 RO USER_IRQ_GENERAL; 6 RO USER_IRQ_SLAVE; 5 RO USER_IRQ_MASTER; 4RO CFG_IRQ_DATA; 3 RO ERR_FLAG 1 2RO MPI_IRQ 1 RO FPSC_IRQ_SLAVE; 0 RO FPSC_IRQ_MASTER |
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