PCM9211 datasheet(14/121 Pages) TI

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PCM9211

SBAS495 – JUNE 2010

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The PCM9211 has two RECOUT signals that can be routed to the MPO port. The respective sources can be

drawn from one of the 12 S/PDIF inputs, or the DIT module.

Channel status, user data, and valid audio data from the S/PDIF stream can be found in various registers or

routed to MPIO pins. In addition, the block start signal can be routed to an I/O pin, so that any postprocessing

DSP can be informed of the start of a frame for decoding data and so forth.

The DIR module in the PCM9211 complies with these digital audio I/F standards:

•

S/PDIF

•

IEC60958 (formerly IEC958)

•

JEITA CPR-1205 (formerly EIAJ CP-1201/340)

•

AES3

•

EBU Tech 3250 (also known as AES/EBU)

In addition, the DIR Module within the PCM9211 also meets and exceeds jitter tolerance specifications defined

by IEC60958-3 for sampling frequencies between 28 kHz and 216 kHz.

Digital Audio Interface Transmitter (DIT)

The DIT (S/PDIF transmitter) is a relatively simple module. The DIT integrated in the PCM9211 is able to

transmit control status and user bits in the data stream, as well as standard 24-bit audio. Channel status, user

data, and Audio Valid bits in the stream are configured on incoming MPIO pins.

The DIT complies with the following audio standards:

•

S/PDIF

•

IEC60958 (formerly IEC958)

•

JEITA CPR-1205 (formerly EIAJ CP-1201/340)

•

AES3

•

EBU Tech 3250 (also known as AES/EBU)

Analog-to-Digital Converter (ADC)

The integrated ADC within the PCM9211 is capable of supporting 24-bit data from 16 kHz up to 96 kHz. The

signal-to-noise ratio (SNR) of the ADC module at 96 kHz is 101 dB.

The PCM9211 contains integrated front-end buffer amplifiers for the ADC, thereby reducing the need for external

amplifiers. The ADC also has several digital features, including digital volume control (adjustable from –100 dB to

+20 dB in 0.5-dB steps), digital mute, and the ability to phase-invert the digital output.

Additionally, interrupts can be generated based on the ADC inputs being larger than user-defined threshold

levels.

In standalone mode, the ADC can be either a clock master or a clock slave.

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