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PCM9211 Datasheet(PDF) 27 Page - Texas Instruments |
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PCM9211 Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 121 page  PCM9211 www.ti.com SBAS495 – JUNE 2010 PLL Clock Source (Built-in PLL and VCO) Details The PCM9211 an has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock from the S/PDIF input signal. The VCO-derived clock is identified as the PLL clock source. When locked, the onboard PLL generates a system clock that synchronizes with the input biphase signal. When unlocked, the PLL generates its own free-run clock (from the VCO). The generated system clocks from the PLL can be set to fixed multiples of the input S/PDIF frequency. Register 30h/PSCK[2:0] can configure the output clock to 128fS, 256fS or 512fS. The PCM9211 also has an automatic default output rate that is calculated based on the incoming S/PDIF frequency. This calculation and rate are controlled by Register 30h/PSCKAUTO. In its default mode, the SCK dividing ratio is configured according to these parameters: • 512fS: 54 kHz and below. • 256fS: 54 kHz to 108 kHz • 128fS: 108 kHz and above (or unlocked) PSCKAUTO takes priority over any settings in PSCK[2:0]. PSCK[2:0] only becomes relevant in the system when the PSCKAUTO Register is set to '0'. The PCM9211 can decode S/PDIF input signals between sampling frequencies of 7 kHz and 216 kHz for all PSCK[2:0] settings. The relationship between the output clock (SCKO, BCKO, LRCKO) at the PLL source and PSCK[2:0] selection is shown in Table 4. Table 4. SCKO, BCKO and LRCKO Frequency Set by PSCK[2:0] OUTPUT CLOCK AT PLL SOURCE PSCK[2:0] SETTING SCKO BCKO LRCKO PSCK2 PSCK1 PSCK0 128fS 64fS fS 0 0 0 256fS 64fS fS 0 1 0 512fS (1) 64fS fS 1 0 0 (1) 512fS SCK is only supported at 108 kHz or lower sampling frequency of incoming biphase signal. In PLL mode, the output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock. The relationship between the sampling frequencies (fS) of the input S/PDIF signal and the frequency of LRCKO, BCKO, and SCKO are shown in Table 5. Table 5. Output Clock Frequency at PLL Lock State LRCK BCK SCK (Depends on PSCK[2:0] Setting) fS 64fS 128fS 256fS 512fS 8 kHz 0.512 MHz 1.024MHz 2.048 MHz 4.096 MHz 11.025 kHz 0.7056 MHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 12 kHz 0.768 MHz 1.536 MHz 3.072 MHz 6.144 MHz 16 kHz 1.024 MHz 2.048 MHz 4.096 MHz 8.192 MHz 22.05 kHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 24 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.288 MHz 32 kHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 44.1 kHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 22.5792 MHz 48 kHz 3.072 MHz 6.144 MHz 12.288 MHz 24.576 MHz 64 kHz 4.096 MHz 8.192 MHz 16.384 MHz 32.768 MHz 88.2 kHz 5.6448 MHz 11.2896 MHz 22.5792 MHz 45.1584 MHz 96 kHz 6.144 MHz 12.288 MHz 24.576 MHz 49.152 MHz 128 kHz 8.192 MHz 16.384 MHz 32.768 MHz N/A 176.4 kHz 11.2896 MHz 22.5792 MHz 45.1584 MHz N/A 192 kHz 12.288 MHz 24.576 MHz 49.152 MHz N/A Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link(s): PCM9211 |
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