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PCM9211 Datasheet(PDF) 30 Page - Texas Instruments |
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PCM9211 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 121 page ![]() B 0L 0L W 0R 0R M 1L 1L W 1R 1R t LATE 17±1BCK BiphaseSignal(IN) BFRAME(OUT) LRCK(OUT) (I S) 2 LRCK(OUT) (AllexceptI S) 2 DATA(OUT) BCKO (OUT) LRCKO (OUT) DOUT (OUT) SCKO (OUT) t SCY t BCH t BCL t BCY t BCDO t CKLR V /2 DD V /2 DD V /2 DD V /2 DD PCM9211 SBAS495 – JUNE 2010 www.ti.com Figure 22 shows the latency time between the input biphase signal and LRCKO/DOUT. Figure 23 illustrates the DIR decoded audio data output timing. SYMBOL DESCRIPTION MIN TYP MAX UNITS tLATE LRCKO/DOUT latency 4/fS s Figure 22. Latency Time Between Input Biphase and LRCKO/DOUT SYMBOL DESCRIPTION MIN TYP MAX UNITS tSCY System clock pulse cycle time 18 ns tCKLR Delay time of BCKO falling edge to LRCKO valid –10 10 ns tBCY BCKO pulse cycle time 1/64fS s tBCH BCKO pulse width high 60 ns tBCL BCKO pulse width low 60 ns tBCDO Delay time of BCKO falling edge to DOUT valid –10 10 ns tR Rising time of all signals 5 ns tF Falling time of all signals 5 ns NOTE: Load capacitance of LRCKO, BCKO, and DOUT pin is 20 pF. DOUT, LRCKO, and BCKO are synchronized with SCKO. Figure 23. DIR Decoded Audio Data Output Timing 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): PCM9211 |
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