Electronic Components Datasheet Search
  English  ▼

X  

PCM9211 Datasheet(PDF) 19 Page - Texas Instruments

Click here to check the latest version.
Part # PCM9211
Description  Integrated DIX, ADC, and Signal Routing: ??Asynchronous Operation (DIR, DIT, ADC) ??Mux and Routing of PCM Data: ??I2S?? Left-Justified, Right-Justified
PDF  121 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM9211 Datasheet(HTML) 19 Page - Texas Instruments

Back Button PCM9211 Datasheet HTML 15Page - Texas Instruments PCM9211 Datasheet HTML 16Page - Texas Instruments PCM9211 Datasheet HTML 17Page - Texas Instruments PCM9211 Datasheet HTML 18Page - Texas Instruments PCM9211 Datasheet HTML 19Page - Texas Instruments PCM9211 Datasheet HTML 20Page - Texas Instruments PCM9211 Datasheet HTML 21Page - Texas Instruments PCM9211 Datasheet HTML 22Page - Texas Instruments PCM9211 Datasheet HTML 23Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 121 page
background image
SystemClock
(SCK)
"L"
"H"
0.8V
2V
t
SCL
t
SCH
t
SCY
PCM9211
www.ti.com
SBAS495 – JUNE 2010
ADC Details
System Clock
The system clock for the ADC of the PCM9211 must be either 256fS or 512fS, where fS is the audio sampling rate
for the ADC (16 kHz to 96 kHz).
Table 3 lists the typical system clock frequencies fSCK for common audio sampling rates. Figure 13 shows the
timing requirements for the system clock inputs.
Table 3. ADC Clock Requirements
BIT CLOCK FREQUENCY
SYSTEM CLOCK FREQUENCY
SAMPLING FREQUENCY
64fS
256fS
512fS
16 kHz
1.024 MHz
4.0960 MHz
8.1920 MHz
32 kHz
2.048 MHz
8.1920 MHz
16.3840 MHz
44.1 kHz
2.8224 MHz
11.2896 MHz
22.5792 MHz
48 kHz
3.072 MHz
12.2880 MHz
24.5760 MHz
88.2 kHz
5.6448 MHz
22.5792 MHz
See (1)
96 kHz
6.144 MHz
24.5760 MHz
See (1)
(1)
This system clock frequency is not supported for the given sampling clock frequency
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
tSCY
System clock cycle time
30
ns
tSCH
System clock high time
0.4 tSCY
ns
tSCL
System clock low time
0.4 tSCY
ns
System clock duty cycle
40
60
%
Note:
This timing requirement is applied when ADC clock source (Register 42h/ADCLK) is AUXIN0, AUXIN1 or AUXIN2.
Figure 13. ADC System Clock Input Timing
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): PCM9211



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com