AD9516-5PCBZ datasheet(29/76 Pages) AD

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AD9516-5

Rev. A | Page 29 of 76

PLL External Loop Filter

An example of an external loop filter for a PLL is shown in

Figure 36. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend on the VCO

frequency, the KVCO, the PFD frequency, the charge pump current,

the desired loop bandwidth, and the desired phase margin. The

loop filter affects the phase noise, loop settling time, and loop

stability. A basic knowledge of PLL theory is helpful for under-

standing loop filter design. ADIsimCLK can help with calculation

of a loop filter according to the application requirements.

CLK/CLK

EXTERNAL

VCO/VCXO

CHARGE

PUMP

AD9516-5

Figure 36. Example of External Loop Filter for PLL

PLL Reference Inputs

The AD9516 features a flexible PLL reference input circuit that

allows a fully differential input or two separate single-ended

inputs. The input frequency range for the reference inputs is

specified in Table 2. Both the differential and the single-ended

inputs are self-biased, allowing for easy ac coupling of input signals.

The differential input and the single-ended inputs share two

pins, REFIN (REF1) and REFIN (REF2). The desired reference

input type is selected and controlled by Register 0x01C (see

and

Table 47

Table 49

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (see Table 2) to prevent

chattering of the input buffer when the reference is slow or missing.

The specification for this voltage level is found in Table 2. The input

hysteresis increases the voltage swing required of the driver to

overcome the offset. The differential reference input can be driven

by either ac-coupled LVDS or ac-coupled LVPECL signals.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine wave or square wave.

Each single-ended input can be independently powered down

when not needed to increase isolation and reduce power. Either

a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential reference input is powered down whenever the

PLL is powered down, or when the differential reference input

is not selected. The single-ended buffers power down when the

PLL is powered down and when their individual power-down

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by a

single-ended signal, the unused side (REFIN) should be decoupled

via a suitable capacitor to a quiet ground.

shows the

equivalent circuit of REFIN.

Figure 37

REF1

REF2

REFIN

150Ω

10kΩ

12kΩ

10kΩ

REFIN

85kΩ

Figure 37. REFIN Equivalent Circuit

Reference Switchover

The AD9516 supports dual single-ended CMOS inputs, as well as

a single differential reference input. In dual single-ended reference

mode, automatic and manual PLL reference clock switching

between REF1 (Pin REFIN) and REF2 (Pin REFIN) is supported.

This feature supports networking and other applications that

require smooth switching of redundant references. When used in

conjunction with the automatic holdover function, the

can achieve a worst-case reference input switchover with an

output frequency disturbance as low as 10 ppm.

AD9516

When using reference switchover, the single-ended reference inputs

should be dc-coupled CMOS levels that are never allowed to go to

high impedance. If the inputs are allowed to go to high impedance,

noise may cause the buffer to chatter, causing false detection of

the presence of a reference. Reference switchover can be performed

manually or automatically. Manual switchover is performed

either through Register 0x01C or by using the REF_SEL pin.

Manual switchover requires the presence of a clock on the reference

input that is being switched to, or that the deglitching feature be

disabled (Register 0x01C[7]). The reference switching logic fails

if this condition is not met, and the PLL does not reacquire.

AD9516-5PCBZ Datasheet(PDF) 29 Page - Analog Devices

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