AD9516-5PCBZ datasheet(41/76 Pages) AD

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AD9516-5

Rev. A | Page 41 of 76

The most common way to execute the SYNC function is to use

the SYNC pin to do a manual synchronization of the outputs.

This requires a low going signal on the SYNC pin, which is held

low and then released when synchronization is desired. The timing

of the SYNC operation is shown in

(using VCO divider)

and

(VCO divider not used). There is an uncertainty

of up to one cycle of the clock at the input to the channel divider

due to the asynchronous nature of the SYNC signal with respect

to the clock edges inside the

. The delay from the

Figure 45

Figure 46

AD9516

SYNC

rising edge to the beginning of synchronized output clocking is

between 14 and 15 cycles of clock at the channel divider input,

plus either one cycle of the VCO divider input (see

or one cycle of the CLK input (see

), depending on

whether the VCO divider is used. Cycles are counted from the

rising edge of the signal.

Figure 45

Figure 46

Another common way to execute the SYNC function is by setting

and resetting the soft SYNC bit at Register 0x230[0] (see Table 47

through Table 57 for details). Both the setting and resetting of

the soft SYNC bit require an update all registers operation

(Register 0x232[0] = 1) to take effect.

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 45. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

INPUT TO CLK

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 46. SYNC Timing When VCO Divider Is Not Used—CLK Input Only

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