AD9516-5PCBZ datasheet(32/76 Pages) AD

32 / 76 page

AD9516-5

Rev. A | Page 32 of 76

The voltage on the capacitor can be sensed by an external

comparator connected to the LD pin. However, there is an

internal LD pin comparator that can be read at the REFMON

pin control (Register 0x01B[4:0]) or the STATUS pin control

(Register 0x017[7:2]) as an active high signal. It is also available

as an active low signal (REFMON, Register 0x01B[4:0] and

STATUS, Register 0x017[7:2]). The internal LD pin comparator

trip point and hysteresis are listed in Table 12.

AD9516-5

REFMON

STATUS

VOUT

110µA

DLD

LD PIN

COMPARATOR

Figure 39. Current Source Lock Detect

External VCXO/VCO Clock Input (CLK/CLK)

CLK is a differential input that can be used to drive the AD9516

clock distribution section. This input can receive up to 2.4 GHz.

The pins are internally self-biased, and the input signal should

be ac-coupled via capacitors.

CLOCK INPUT

STAGE

CLK

5kΩ

2.5kΩ

Figure 40. CLK Equivalent Input Circuit

The CLK/CLK input can be used either as a distribution only

input (with the PLL off), or as a feedback input for an external

VCO/VCXO using the PLL. The CLK/CLK input can be used

for frequencies up to 2.4 GHz.

Holdover

The AD9516 PLL has a holdover function. Holdover is

implemented by putting the charge pump into a high impedance

state. This is useful when the PLL reference clock is lost. Holdover

mode allows the VCO to maintain a relatively constant frequency

even though there is no reference clock. Without this function,

the charge pump is placed into a constant pump-up or pump-

down state, resulting in a large VCO frequency shift. Because

the charge pump is placed in a high impedance state, any leakage

that occurs at the charge pump output or the VCO tuning node

causes a drift of the VCO frequency. This can be mitigated by

using a loop filter that contains a large capacitive component

because this drift is limited by the current leakage induced slew

rate (ILEAK/C) of the VCO control voltage. For most applications,

the frequency is sufficient for 3 sec to 5 sec.

Both a manual holdover mode, using the SYNC pin, and an

automatic holdover mode are provided. To use either function,

the holdover function must be enabled (Register 0x01D[0] and

Manual Holdover Mode

A manual holdover mode can be enabled that allows the user

to place the charge pump into a high impedance state when the

SYNC pin is asserted low. This operation is edge sensitive, not

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

state, take the SYNC pin high. The charge pump then leaves the

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

pump events from occurring during the time between SYNC

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state as long as there is

no reference clock present.

The B counter (in the N divider) is reset synchronously with the

charge pump leaving the high impedance state on the reference

path PFD event. This helps align the edges out of the R and N

dividers for faster settling of the PLL. Because the prescaler is

not reset, this feature works best when the B and R numbers are

close because this results in a smaller phase difference for the

loop to settle out.

When using this mode, set the channel dividers to ignore the

SYNC pin (at least after an initial SYNC event). If the dividers are

not set to ignore the SYNC pin, the distribution outputs turn off

each time SYNC is taken low to put the part into holdover.

AD9516-5PCBZ Datasheet(PDF) 32 Page - Analog Devices

AD9516-5PCBZ Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL