AD9516-5PCBZ datasheet(33/76 Pages) AD

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AD9516-5

Rev. A | Page 33 of 76

Automatic/Internal Holdover Mode

When enabled, this function automatically puts the charge pump

into a high impedance state when the loop loses lock. The

assumption is that the only reason that the loop loses lock is due

to the PLL losing the reference clock; therefore, the holdover

function puts the charge pump into a high impedance state to

maintain the VCO frequency as close as possible to the original

frequency before the reference clock disappears.

See Figure 41 for a flowchart of the internal/automatic holdover

function operation.

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the

DLD, ALD, or current source LD (CSDLD) mode. It is possible

to disable the LD comparator (Register 0x01D[3]), which causes

the holdover function to always sense LD as high. If DLD is

used, it is possible for the DLD signal to chatter somewhat while

the PLL is reacquiring lock. The holdover function may retrigger,

thereby preventing the holdover mode from ever terminating.

Use of the current source lock detect mode is recommended to

avoid this situation (see the Current Source Digital Lock Detect

section).

When in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N divider)

is reset synchronously with the charge pump leaving the high

impedance state on the reference path PFD event. This helps to

align the edges out of the R and N dividers for faster settling of

the PLL and reduce frequency errors during settling. Because the

prescaler is not reset, this feature works best when the B and R

numbers are close because this results in a smaller phase difference

for the loop to settle out.

After leaving holdover, the loop then reacquires lock, and the

LD pin must charge (if Register 0x01D[3] = 1) before it can

re-enter holdover (CP high impedance).

The holdover function always responds to the state of the currently

selected reference (Register 0x01C). If the loop loses lock during a

reference switchover (see the Reference Switchover section),

holdover is triggered briefly until the next reference clock edge

at the PFD.

YES

PLL ENABLED

DLD == LOW

WAS

LD PIN == HIGH

WHEN DLD WENT

LOW?

HIGH IMPEDANCE

CHARGE PUMP

REFERENCE

EDGE AT PFD?

RELEASE

CHARGE PUMP

HIGH IMPEDANCE

DLD == HIGH

LOOP OUT OF LOCK. DIGITAL LOCK

DETECT SIGNAL GOES LOW WHEN THE

LOOP LEAVES LOCK AS DETERMINED

BY THE PHASE DIFFERENCE AT THE

INPUT OF THE PFD.

ANALOG LOCK DETECT PIN INDICATES

LOCK WAS PREVIOUSLY ACHIEVED.

VOLTAGE WITH HOLDOVER.

VOLTAGE,TREAT LD PIN AS ALWAYS HIGH.

CHARGE PUMP IS MADE

HIGH IMPEDANCE.

PLL COUNTERS CONTINUE

OPERATING NORMALLY.

CHARGE PUMP REMAINS HIGH

IMPEDANCE UNTIL THE REFERENCE

HAS RETURNED.

TAKE CHARGE PUMP OUT OF

HIGH IMPEDANCE. PLL CAN

NOW RESETTLE.

WAIT FOR DLD TO GO HIGH. THIS TAKES

5 TO 255 CYCLES (PROGRAMMING OF

THE DLD DELAY COUNTER) WITH THE

REFERENCE AND FEEDBACK CLOCKS

INSIDE THE LOCK WINDOW AT THE PFD.

THIS ENSURES THAT THE HOLDOVER

FUNCTION WAITS FOR THE PLL TO SETTLE

AND LOCK BEFORE THE HOLDOVER

FUNCTION CAN BE RETRIGGERED.

YES

Figure 41. Flowchart of Automatic/Internal Holdover Mode

AD9516-5PCBZ Datasheet(PDF) 33 Page - Analog Devices

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