AD9516-5PCBZ datasheet(40/76 Pages) AD

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AD9516-5

Rev. A | Page 40 of 76

Let

Δt = delay (in seconds).

Φx.y = 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +

1 × PO[0].

TX.1 = period of the clock signal at the input to DX.1 (in seconds).

TX.2 = period of the clock signal at the input to DX.2 (in seconds).

Case 1

When Φx.1 ≤ 15 and Φx.2 ≤ 15:

Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2

Case 2

When Φx.1 ≤ 15 and Φx.2 ≥ 16:

Δt = ΦX.1 × TX.1 + (ΦX.2 – 16 + MX.2 + 1) × TX.2

Case 3

When ΦX.1 ≥ 16 and ΦX.2 ≤ 15:

Δt = (ΦX.1 − 16 + MX.1 + 1) × TX.1 + ΦX.2 × TX.2

Case 4

When ΦX.1 ≥ 16 and ΦX.2 ≥ 16:

Δt =

(ΦX.1 − 16 + MX.1 + 1) × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2

Fine Delay Adjust (Divider 3 and Divider 4)

Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes

an analog delay element that can be programmed to give variable

time delays (Δt) in the clock signal at that output.

DIVIDER

X.2

DIVIDER

X.1

∆t

OUTM

BYPASS

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

∆t

OUTN

BYPASS

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

OUTPUT

DRIVERS

CLK

VCO

DIVIDER

Figure 44. Fine Delay (OUT6 to OUT9)

The amount of delay applied to the clock signal is determined

by programming four registers per output (see Table 41).

Table 41. Setting Analog Fine Delays

OUTPUT

(LVDS/CMOS)

Ramp

Capacitors

Ramp

Current

Delay

Fraction

Delay

Bypass

OUT6

0x0A1[5:3]

0x0A1[2:0]

0x0A2[5:0]

0x0A0[0]

OUT7

0x0A4[5:3]

0x0A4[2:0]

0x0A5[5:0]

0x0A3[0]

OUT8

0x0A7[5:3]

0x0A7[2:0]

0x0A8[5:0]

0x0A6[0]

OUT9

0x0AA[5:3]

0x0AA[2:0]

0x0AB[5:0]

0x0A9[0]

Calculating the Fine Delay

The following values and equations are used to calculate the

delay of the delay block.

IRAMP (μA) = 200 × (Ramp Current + 1)

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;

001 = 2 + 1 = 3; 111 = 0 + 1 = 1.

Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286



1600

0.34





























RAMP

Caps

No.

Offset

Delay Full Scale (ns) = Delay Range + Offset

Fine Delay (ns) =

Delay Range × Delay Fraction × (1/63) + Offset

Note that only delay fraction values up to 47 decimal (101111b;

0x02F) are supported.

In no case can the fine delay exceed one-half of the output clock

period. If a delay longer than half of the clock period is attempted,

the output stops clocking.

The delay function adds some jitter that is greater than that

specified for the nondelayed output. This means that the delay

function should be used primarily for clocking digital chips, such

as FPGA, ASIC, DUC, and DDC. An output with this delay

enabled may not be suitable for clocking data converters. The

jitter is higher for long full scales because the delay block uses a

ramp and trip points to create the variable delay. A slower ramp

time produces more time jitter.

Synchronizing the Outputs—SYNC Function

The AD9516 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and, subsequently, releasing

these outputs to continue clocking at the same instant with the

preset conditions applied. This allows for the alignment of the

edges of two or more outputs or for the spacing of edges

according to the coarse phase offset settings for two or more

outputs.

Synchronization of the outputs is executed in several ways:



By forcing the SYNC pin and then releasing it (manual sync)



By setting and then resetting any one of the following three

bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit

(Register 0x000[2] [mirrored]), or the power-down

distribution reference bit (Register 0x230[1])



By executing synchronization of the outputs as part of the

chip power-up sequence



By forcing the RESET pin low, then releasing it (chip reset)



By forcing the PD pin low, then releasing it (chip power-down)

AD9516-5PCBZ Datasheet(PDF) 40 Page - Analog Devices

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