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AD9516-5PCBZ Datasheet(PDF) 47 Page - Analog Devices

Part # AD9516-5PCBZ
Description  14-Output Clock Generator
PDF  76 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9516-5PCBZ Datasheet(HTML) 47 Page - Analog Devices

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AD9516-5
Rev. A | Page 47 of 76
CS
SCLK
SDIO
tHIGH
tLOW
tSCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
Figure 57. Serial Control Port Timing—Write
Table 45. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and the rising edge of SCLK
tDH
Hold time between data and the rising edge of SCLK
tCLK
Period of the clock
Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle)
tS
Setup time between the SCLK rising edge and the CS rising edge (end of communication cycle)
tC
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 55)



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