AD9516-5PCBZ datasheet(4/76 Pages) AD

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AD9516-5

Rev. A | Page 4 of 76

SPECIFICATIONS

Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.

Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

3.135

3.3

3.465

3.3 V ± 5%

VS_LVPECL

2.375

Nominally 2.5 V to 3.3 V ± 5%

VCP

5.25

Nominally 3.3 V to 5.0 V ± 5%

RSET Pin Resistor

4.12

kΩ

Sets internal biasing currents; connect to ground

CPRSET Pin Resistor

2.7

5.1

kΩ

Sets internal CP current range, nominally 4.8 mA

(CP_lsb = 600 μA); actual current can be calculated by:

CP_lsb = 3.06/CPRSET; connect to ground

PLL CHARACTERISTICS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Differential mode (can accommodate single-ended

input by ac grounding undriven input)

Input Frequency

250

MHz

Frequencies below about 1 MHz should be dc-coupled;

be careful to match VCM (self-bias voltage)

Input Sensitivity

250

mV p-p

PLL figure of merit (FOM) increases with increasing slew

rate; see Figure 13

Self-Bias Voltage, REFIN

1.35

1.60

1.75

Self-bias voltage of REFIN1

Self-Bias Voltage, REFIN

1.30

1.50

1.60

Self-bias voltage of REFIN1

Input Resistance, REFIN

4.0

4.8

5.9

kΩ

Self-biased1

Input Resistance, REFIN

4.4

5.3

6.4

kΩ

Self-biased1

Dual Single-Ended Mode (REF1, REF2)

Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled)

250

MHz

Slew rate > 50 V/μs

Input Frequency (DC-Coupled)

250

MHz

Slew rate > 50 V/μs; CMOS levels

Input Sensitivity (AC-Coupled)

0.8

V p-p

Should not exceed VS p-p

Input Logic High

2.0

Input Logic Low

0.8

Input Current

−100

+100

μA

Input Capacitance

Each pin, REFIN/REFIN (REF1/REF2)

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

100

MHz

Antibacklash pulse width = 1.3 ns, 2.9 ns

MHz

Antibacklash pulse width = 6.0 ns

Antibacklash Pulse Width

1.3

2.9

6.0

CHARGE PUMP (CP)

ICP Sink/Source

Programmable

High Value

4.8

With CPRSET = 5.1 kΩ

Low Value

0.60

Absolute Accuracy

2.5

CPV = VCP/2

CPRSET Range

2.7/10

kΩ

ICP High Impedance Mode Leakage

Sink-and-Source Current Matching

0.5 < CPV < VCP − 0.5 V

ICP vs. CPV

1.5

0.5 < CPV < VCP − 0.5 V

ICP vs. Temperature

VCP = VCP/2 V

AD9516-5PCBZ Datasheet(PDF) 4 Page - Analog Devices

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