AD9516-5PCBZ datasheet(16/76 Pages) AD

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AD9516-5

Rev. A | Page 16 of 76

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

REFMON

VCP

STATUS

REF_SEL

SYNC

CLK

SCLK

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

GND

OUT2

VS_LVPECL

OUT3

GND

OUT9 (OUT9B)

OUT9 (OUT9A)

OUT8 (OUT8B)

OUT8 (OUT8A)

AD9516-5

TOP VIEW

(Not to Scale)

LVPECL LVPECL

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

Figure 6. Pin Configuration

Table 17. Pin Function Descriptions

Pin No.

Input/

Output

Pin Type

Mnemonic

Description

1, 11, 12, 30,

31, 32, 38,

49, 50, 51,

57, 60, 61

Power

3.3 V Power Pins.

3.3 V CMOS

REFMON

Reference Monitor (Output). This pin has multiple selectable outputs;

see Table 49, Register 0x01B.

3.3 V CMOS

Lock Detect (Output). This pin has multiple selectable outputs; see Table 49,

Power

VCP

Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V.

Loop filter

Charge Pump (Output). This pin connects to an external loop filter. This pin can

be left unconnected if the PLL is not used.

3.3 V CMOS

STATUS

Status (Output). This pin has multiple selectable outputs; see Table 49,

3.3 V CMOS

REF_SEL

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor.

3.3 V CMOS

SYNC

Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has

an internal 30 kΩ pull-up resistor.

9, 10, 15, 18,

19, 20

N/A

No Connection. These pins can be left floating.

Along with CLK, this is the differential input for the clock distribution section.

Differential

clock input

CLK

Differential

clock input

CLK

Along with CLK, this is the differential input for the clock distribution section.

If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass

capacitor from CLK to ground.

AD9516-5PCBZ Datasheet(PDF) 16 Page - Analog Devices

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