AD9516-5PCBZ datasheet(37/76 Pages) AD

37 / 76 page

AD9516-5

Rev. A | Page 37 of 76

Table 32. Channel Divider Output Duty Cycle When the

VCO Divider Is Not Used

Output Duty Cycle

Input Clock

Duty Cycle

N + M + 2

DCCOFF = 1

DCCOFF = 0

Any

Channel

divider

bypassed

1 (divider

bypassed)

Same as input

duty cycle

Any

Even

(N + 1)/

(M + N + 2)

50%, requires M = N

50%

Odd

(N + 1)/

(M + N + 2)

50%, requires

M = N + 1

Odd

(N + 1)/

(M + N + 2)

(N + 1 + X%)/(2 × N + 3),

requires M = N + 1

If the CLK input is routed directly to the output, the duty cycle of

the output is the same as the CLK input.

Phase Offset or Coarse Time Delay (0, 1, and 2)

Each channel divider allows for a phase offset, or a coarse time

delay, to be programmed by setting register bits (see Table 33).

These settings determine the number of cycles (successive

rising edges) of the channel divider input frequency by which to

offset, or delay, the rising edge of the output of the divider. This

delay is with respect to a nondelayed output (that is, with a

phase offset of zero). The amount of the delay is set by five bits

loaded into the phase offset (PO) register, plus the start high

(SH) bit for each channel divider. When the start high bit is set,

the delay is also affected by the number of low cycles (M) that

are programmed for the divider.

The sync function must be used to make phase offsets effective

(see the Synchronizing the Outputs—SYNC Function section).

Table 33. Setting Phase Offset and Division for Divider 0,

Divider 1, and Divider 21

Divider

Start

High (SH)

Phase

Offset (PO)

Low

Cycles (M)

High

Cycles (N)

0x191[4]

0x191[3:0]

0x190[7:4]

0x190[3:0]

0x194[4]

0x194[3:0]

0x193[7:4]

0x193[3:0]

0x197[4]

0x197[3:0]

0x196[7:4]

0x196[3:0]

1 Note that the value stored in the register = # of cycles minus 1. For example,

Let

Δt = delay (in seconds).

Δc = delay (in cycles of clock signal at input to DX).

TX = period of the clock signal at the input of the divider, DX (in

seconds).

Φ =

16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]

The channel divide-by is set as N = high cycles and M = low

cycles.

Case 1

For Φ ≤ 15:

Δt = Φ × TX

Δc = Δt/TX = Φ

Case 2

For Φ ≥ 16:

Δt = (Φ − 16 + M + 1) × TX

Δc = Δt/TX

By giving each divider a different phase offset, output-to-output

delays can be set in increments of the channel divider input

clock cycle. Figure 43 shows the results of setting such a coarse

offset between outputs.

CHANNEL DIVIDER OUTPUTS

DIV = 4, DUTY = 50%

234

567

89 10 11 12 13 14 15

DIVIDER 0

DIVIDER 1

DIVIDER 2

CHANNEL

DIVIDER INPUT

SH = 0

PO = 0

SH = 0

PO = 1

SH = 0

PO = 2

1 × Tx

2 × Tx

Figure 43. Effect of Coarse Phase Offset (or Delay)

Channel Dividers—LVDS/CMOS Outputs

Channel Divider 3 and Channel Divider 4 each drive a pair of

LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).

Alternatively, each of these LVDS differential outputs can be

configured individually as a pair (A and B) of CMOS single-

ended outputs, providing for up to eight CMOS outputs. By default,

the B output of each pair is off but can be turned on as desired.

Channel Divider 3 and Channel Divider 4 each consist of two

cascaded, 2 to 32, frequency dividers. The channel frequency

division is DX.1 × DX.2, or up to 1024. Divide-by-1 is achieved by

bypassing one or both of these dividers. Both of the dividers also

have DCC enabled by default, but this function can be disabled,

if desired, by setting the DCCOFF bit of the channel. A coarse

phase offset or delay is also programmable (see the Phase Offset

or Coarse Time Delay (Divider 3 and Divider 4) section). The

channel dividers operate up to 1600 MHz. The features and

settings of the dividers are selected by programming the

appropriate setup and control registers (see Table 47 and Table 48

through Table 57).

Table 34. Setting Division (DX) for Divider 3 and Divider 41

Divider

Bypass

DCCOFF

3.1

0x199[7:4]

0x199[3:0]

0x19C[4]

0x19D[0]

3.2

0x19B[7:4]

0x19B[3:0]

0x19C[5]

0x19D[0]

4.1

0x19E[7:4]

0x19E[3:0]

0x1A1[4]

0x1A2[0]

4.2

0x1A0[7:4]

0x1A0[3:0]

0x1A1[5]

0x1A2[0]

1 Note that the value stored in the register = # of cycles minus 1. For example,

AD9516-5PCBZ Datasheet(PDF) 37 Page - Analog Devices

AD9516-5PCBZ Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL