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AD9516-5PCBZ Datasheet(PDF) 69 Page - Analog Devices |
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AD9516-5PCBZ Datasheet(HTML) 69 Page - Analog Devices |
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69 / 76 page ![]() AD9516-5 Rev. A | Page 69 of 76 Reg. Addr. (Hex) Bits Name Description 2 Divider 4 force high Forces Divider 4 output high. Requires that the Divider 4 nosync bit (Bit 3) also be set. 0: forces low (default). 1: forces high. 1 Start High Divider 4.2 Divider 4.2 starts high/low. 0: starts low (default). 1: starts high. 0 Start High Divider 4.1 Divider 4.1 starts high/low. 0: starts low (default). 1: starts high. 0x1A2 0 Divider 4 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Table 55. VCO Divider and CLK Input Reg. Addr. (Hex) Bits Name Description 0x1E0 [2:0] VCO divider 2 1 0 Divide 0 0 0 2 0 0 1 3 0 1 0 4 (default) 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 Output static 1 1 1 Output static 0x1E1 4 Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). 0: normal operation (default). 1: powers down. 0 Bypass VCO divider Bypasses or uses the VCO divider. 0: uses VCO divider (default). 1: bypasses VCO divider. Table 56. System Reg. Addr. (Hex) Bits Name Description 230 2 Power-down SYNC Powers down the sync function. 0: normal operation of the sync function (default). 1: powers down the SYNC circuitry. 1 Power-down distribution reference Powers down the reference for distribution section. 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section. 0 Soft SYNC The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1- to-0 transition triggers a SYNC. 0: same as SYNC high (default). 1: same as SYNC low. |
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