AD9516-5PCBZ datasheet(25/76 Pages) AD

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AD9516-5

Rev. A | Page 25 of 76

THEORY OF OPERATION

PROGRAMMABLE

N DELAY

REFIN (REF1)

REFIN (REF2)

CLK

REF1

REF2

AD9516-5

STATUS

DIVIDER

VCO STATUS

PROGRAMMABLE

R DELAY

REFERENCE

SWITCHOVER

REF_SEL

CPRSET VCP

GND

RSET

DISTRIBUTION

REFERENCE

REFMON

STATUS

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CHARGE

PUMP

HOLD

OUT0

OUT1

OUT0

OUT1

LVPECL

DIVIDE BY

1 TO 32

OUT2

OUT3

OUT2

OUT3

LVPECL

DIVIDE BY

1 TO 32

OUT4

OUT5

OUT4

OUT5

LVPECL

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT6 (OUT6A)

OUT6 (OUT6B)

∆t

OUT7 (OUT7A)

OUT7 (OUT7B)

∆t

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT8 (OUT8A)

OUT8 (OUT8B)

∆t

OUT9 (OUT9A)

OUT9 (OUT9B)

∆t

DIVIDE BY

1 TO 32

DIVIDE BY

2, 3, 4, 5, OR 6

SYNC

RESET

SCLK

SDIO

SDO

DIGITAL

LOGIC

SERIAL

CONTROL

PORT

Figure 33. Clock Distribution or External VCO < 1600 MHz (Mode 1)

OPERATIONAL CONFIGURATIONS

The AD9516 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 47 and Table 48 through Table 57). Each section or

function must be individually programmed by setting the

appropriate bits in the corresponding control register or registers.

Mode 1—Clock Distribution or External VCO < 1600 MHz

Mode 1 bypasses the VCO divider. Mode 1 can be used only

with an external clock source of <1600 MHz, due to the maximum

input frequency allowed at the channel dividers.

For clock distribution applications where the external clock is less

than 1600 MHz, use the register settings shown in Table 18.

Table 18. Settings for Clock Distribution < 1600 MHz

Description

0x010[1:0] = 01b

PLL asynchronous power-down (PLL off )

0x1E1[0] = 1b

Bypass the VCO divider as source for

distribution section

When using the internal PLL with an external VCO of <1600 MHz,

the PLL must be turned on.

AD9516-5PCBZ Datasheet(PDF) 25 Page - Analog Devices

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