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AD9516-5PCBZ Datasheet(PDF) 49 Page - Analog Devices |
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AD9516-5PCBZ Datasheet(HTML) 49 Page - Analog Devices |
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49 / 76 page  AD9516-5 Rev. A | Page 49 of 76 REGISTER MAPS REGISTER MAP OVERVIEW Register addresses that are not listed in Table 47 (as well as ones marked unused) are not used and writing to those registers has no effect. The user should write the default value only to the register addresses marked reserved. Table 47. Register Map Overview Ref. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Serial Port Configuration 0x000 Serial port configuration SDO active LSB first Soft reset Long instruction Long instruction Soft reset LSB first SDO active 0x18 0x001 Blank 0x002 Reserved 0x003 Part ID Part ID (read only) 0x01 0x004 Readback control Blank Read back active registers 0x00 PLL 0x010 PFD and charge pump PFD polarity Charge pump current Charge pump mode PLL power-down 0x7D 0x011 R Counter 14-bit R divider, Bits[7:0] (LSB) 0x01 0x012 Blank 14-bit R divider, Bits[13:8] (MSB) 0x00 0x013 A counter Blank 6-bit A counter 0x00 0x014 B counter 13-bit B counter, Bits[7:0] (LSB) 0x03 0x015 Blank 13-bit B counter, Bits[12:8] (MSB) 0x00 0x016 PLL Control 1 Set CP pin to VCP/2 Reset R counter Reset A and B counters Reset all counters B counter bypass Prescaler P 0x06 0x017 PLL Control 2 STATUS pin control Antibacklash pulse width 0x00 0x018 PLL Control 3 Reserved Lock detect counter Digital lock detect window Disable digital lock detect Reserved 0x06 0x019 PLL Control 4 R, A, B counters SYNC pin reset R path delay N path delay 0x00 0x01A PLL Control 5 Reserved Reference frequency monitor threshold LD pin control 0x00 0x01B PLL Control 6 CLK frequency monitor REF2 (REFIN) frequency monitor REF1 (REFIN) frequency monitor REFMON pin control 0x00 0x01C PLL Control 7 Disable switchover deglitch Select REF2 Use REF_SEL pin Reserved REF2 power-on REF1 power-on Differential reference 0x00 0x01D PLL Control 8 Reserved PLL status register disable LD pin comparator enable Holdover enable External holdover control Holdover enable 0x00 0x01E PLL Control 9 Reserved 0x00 0x01F PLL readback (read-only) Reserved Holdover active REF2 selected CLK frequency > threshold REF2 frequency > threshold REF1 frequency > threshold Digital lock detect N/A 0x020 to 0x04F Blank |
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