AM8530 datasheet(109/194 Pages) AMD

109 / 194 page

Support Circuitry Programming

AMD

5–15

5.5.4

DPLL Initialization

Initialization of the DPLL may be done at any time during the initialization sequence, but

should probably be done after the clock modes have been selected in WR11, and before

the receiver and transmitter are enabled.

When initializing the DPLL the clock source should be selected first, followed by the se-

lection of the operating mode. At this point the DPLL, may be enabled by issuing the En-

ter Search Mode command in WR14. Note that a channel or hardware reset disables the

DPLL, selects the

RTxC pin as the clock source for the DPLL, and places it in the NRZI

mode.

Note that the DPLL is not free running if it is in search mode. Unless the DPLL receives a

continuous stream of data, it will lose synchronization and enter search mode. It is there-

fore recommended that the clock input of the transmitter is fed from a continuous clock

source other than the DPLL unless it can be guaranteed the DPLL always receives

enough data to stay synchronized.

5.5.5

Am85C30-16 DPLL OPERATION AT 32 MHz

5.5.5.1

Introduction

The Digital Phase-Locked Loop (DPLL) for the Am85C30-16 can operate at twice the

data sheet frequency (32 MHz). The DPLL is used to recover clock information from a FM

data stream. This enhancement is available for

commercial product only.

All Am85C30-16 devices are tested to guarantee 32 MHz DPLL capability.

5.5.5.2

Benefit

The customer can transmit and receive serial data at 2 mb/s in FM mode. This is twice

the data rate specified in the data sheet. This is over three times what the competition

can do. As specified in the competition’s data sheet, 10 MHz part can only handle a

10 MHz clock for the DPLL. The Am85C30-16 DPLL can run at 32 MHz for both synchro-

nous (SDLC) and asynchronous modes with FM encoding. This eliminates the need for

an external DPLL and allows the user to utilize FM encoding at higher data rates.

5.5.5.3

Applications

The increased data rate of 2 mb/s is ideal for both factory and office automation applica-

tions including Local Area Networks as well as other RS485 and RS422 applications.

5.5.5.4

Description

An external 32 MHz, 50% duty cycle, TTL compatible signal to the

RTxC pin provides the

clock for the DPLL. The PCLK remains at 16 MHz. The rest of the setup is described in

detail in the previous section of this technical manual.

5.5.5.5

Competition

The competition’s data sheet for their 85C30 limits the clock for the DPLL to less than

10 MHz. This translates to only 0.625 mb/s for FM transmission and reception. The

Am85C30-16 transmits and receives FM data at 2.0 mb/s—over three times faster than

the competition’s part.

5.6

DIAGNOSTIC MODES

The SCC contains two other features useful for diagnostic purposes controlled by bits in

WR14. These are Local Loopback and Auto Echo.

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