AM8530 datasheet(106/194 Pages) AMD

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AMD

5–12

Bit Cell

Count 16

811

Correction

Add One Count

Subtract One Count

No Change

DPLL Out

Figure 5–6. DPLL in NRZI Mode

However, if the transition marking a bit cell boundary occurs between the middle of count

16 and count 31 the DPLL is sampling the data too early in the bit cell. In response to this

the DPLL extends its count by one during the next 0 to 31 counting cycle, which effec-

tively moves the edge of the clock that samples the receive data closer to the center of

the bit cell. In a similar manner, if the transition occurs between count 0 and the middle of

count 15, the output of the DPLL is sampling the data to late in the bit cell. To correct this,

the DPLL shortens its count by one during the next 0 to 31 counting cycle, which effec-

tively moves the edge of the clock that samples the receive data closer to the center of

the bit cell.

In NRZI mode, if the DPLL does not see any transition during a counting cycle, no adjust-

ment is made in the following counting cycle. If an adjustment to the counting cycle is

necessary the DPLL modifies count five, either deleting it or doubling it. Thus only the

Low time of the DPLL output will be lengthened or shortened. While the DPLL is in search

mode, the counter remains at count 16, where the DPLL outputs are both High. An exam-

ple of the DPLL in operation is shown in Figure 5–7.

5.5.3.2

FM Mode

In FM mode, the clock supplied to the DPLL must be 16 times the data rate. In this mode

the transmit clock output of the DPLL lags the receive clock output by 90 degrees. This is

necessary to make the transmit and receive bit cell boundaries coincide, since the receive

clock must sample the data one-fourth and three-fourths of the way through the bit cell. In

FM mode the DPLL requires a transition in every bit cell, and if this transition is not pre-

sent in two consecutive sampled bit cells, the DPLL automatically enters search mode.

The DPLL uses the clock supplied, along with the receive data, to construct receive and

transmit clock outputs that are phased to receive and transmit data properly. In FM mode

the counter in the DPLL still counts from 0 to 31 but now each cycle corresponds to 2 bit

cells. In order to make adjustments and remain in phase with the receive data, the DPLL

divides a pair of bit cells into five regions, making the adjustment to the counter depend-

ent upon which region the transition on the receive data input occurred. This is shown in

Figure 5–8.

Ordinarily, a bit cell boundary will occur between count 15 or count 16, and the DPLL re-

ceive output will cause the data to be sampled at one-fourth and three-fourths of the way

through the bit cell. The DPLL actually allows the transition marking a bit cell boundary to

occur anywhere during the second half of count 15 or the first half of count 16 without

making a correction to its count cycle.

AM8530 Datasheet(PDF) 106 Page - Advanced Micro Devices

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