AM8530 datasheet(103/194 Pages) AMD

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AMD

5–9

5.3.3

BRG Initialization

Initializing the BRG is done in four steps. First, the time-constant is determined and

loaded into WR12 and WR13. Next, the processor must select the clock source for the

BRG by writing to bit D1 of WR14. Finally, the BRG is enabled by setting bit D0 of WR14

to ‘1’. Note that the first write to WR14 is not necessary after a hardware reset if the clock

source is to be the

RTxC pin. This is because a hardware reset automatically selects the

RTxC pin as the BRG clock source.

5.4

DATA ENCODING/DECODING

The SCC provides four data encoding methods, selected by bits D6 and D5 in WR10. An

example of these four methods is shown in Figure 5–4. Encoding may be used for asyn-

chronous or synchronous data as long as the clock mode is x1. Note that the data encod-

ing method selected is active even though the transmitter or receiver may be idling or dis-

abled.

001

Data

NRZ

NRZI

FM1

(BiPhase Mark)

FM0

(BiPhase Space)

Bit Cell Level:

High = 1

Low = 0

No Change = 1

Change = 0

Bit Center Transition:

Transition = 1

No Transition = 0

Manchester

No Transition = 1

Transition = 0

High

→Low = 1

Low

→High = 0

Figure 5–4. Data Encoding

5.4.1

NRZ (Non-Return to Zero)

In NRZ encoding a ‘1’ is represented by a High level and a ‘0’ is represented by a Low

level. In this encoding method only a minimal amount of clocking information is available

in the data stream in the form of transitions on bit-cell boundaries. In an arbitrary data

pattern this may not be sufficient to generate a clock for the data from the data itself.

5.4.2

NRZI (Non-Return to Zero Inverted)

In NRZI encoding a ‘1’ is represented by no change in the level and a ‘0’ is represented

by a change in the level. As in NRZ only a minimal amount of clocking information is

available in the data stream, in the form of transitions on bit cell boundaries. In an arbi-

trary data pattern this may not be sufficient to generate a clock for the data from the data

itself. In the case of SDLC Mode operation, where the number of consecutive ‘1’s in the

data stream is limited, a minimum number of transitions to generate a clock are guar-

anteed.

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