AM8530 datasheet(105/194 Pages) AMD

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Support Circuitry Programming

AMD

5–11

5.5.1

DPLL Clock Source

The clock for the DPLL is selected by two of the commands in WR14. One command se-

lects the output of the BRG as the clock source, and the other command selects the

RTxC pin as the clock source, independent of whether the RTxC pin is a simple input or

part of the crystal oscillator circuit. Note that in order to avoid metastable problems in the

counter, the clock source selection should be made only while the DPLL is disabled, since

arbitrarily narrow pulses can be generated at the output of the multiplexer when it

changes status.

5.5.2

DPLL Enabling

The DPLL is enabled by issuing the Enter Search Mode command in WR14. This com-

mand is also used to reset the DPLL to a known state if it is suspected that synchroniza-

tion has been lost. When used to enable the DPLL, the Enter Search Mode command

unlocks the counter, which is held while the DPLL is disabled, and enables the edge de-

tector. If the DPLL is already enabled when this command is issued, the DPLL also enters

Search mode.

While in Search mode, the counter is held at a specific count and no outputs are pro-

vided. The DPLL remains in this status until an edge is detected in the receive data

stream. This first edge is assumed to occur on a bit cell boundary, and the DPLL will be-

gin providing an output to the receiver that will properly sample the data. As long as no

other edges are detected, the DPLL output clock will free run at a frequency equal to the

DPLL clock source divided by 32 without any phase jitter. Upon detecting another edge

the DPLL will adjust the output clock to remain in phase with the received data by adding

or subtracting a count of one. This will result in a phase jitter of

±5.63° on the DPLL out-

put. Because the DPLL uses both edges of the incoming data to compare with its clock

source, a mark-space deviation of no greater than

±1.5% (from 50%) should be main-

tained at the interface. If the first edge that the DPLL sees does not occur on a bit cell

boundary, the DPLL will eventually lock on to the receive data but it will take longer to do

so.

5.5.3

DPLL Modes

The DPLL may be programmed to operate in either NRZI or FM modes, as selected by a

command in WR14. Note that as in the case of the DPLL clock source selection, the

mode of operation should only be changed while the DPLL is disabled to prevent unpre-

dictable results.

5.5.3.1

NRZI Mode

In NRZI mode, the clock supplied to the DPLL must be 32 times the data rate. In this

mode the transmit and receive clock outputs of the DPLL are identical, and the clocks are

phased so that the receiver samples the data in the middle of the bit cell. In NRZI mode,

the DPLL does not require a transition in every bit cell, so this is useful for recovering the

clocking information from NRZ and NRZI data streams.

The DPLL uses the x32 clock along with the receive data, to construct receive and trans-

mit clock outputs that are phased to properly receive and transmit data.

To do this, the DPLL divides each bit cell into two regions, and makes an adjustment to

the count cycle of the 5-bit counter dependent upon in which region a transition on the

receive data input occurred. This is shown in Figure 5–6. Ordinarily, a bit cell boundary

will occur between count 15 and count 16, and the DPLL output will cause the data to be

sampled in the middle of the bit cell. The DPLL actually allows the transition marking a bit

cell boundary to occur anywhere during the second half of count 15 or the first half of

count 16 without making a correction to its count cycle.

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