AM8530 datasheet(146/194 Pages) AMD

146 / 194 page

AMD

6–36

D7 D6 D5 D4 D3 D2 D1 D0

Channel A EXT/STAT IP

Channel A Tx IP

Channel A Rx IP

Channel B EXT/STAT IP

Channel B Tx IP

Channel B Rx IP

Always 0 in B Channel

Figure 6–21. Read Register 3

6.3.5

Read Register 6

When the SCC is programmed for SDLC operation and bit D2 of WR15 is set to ‘1’, RR6

contains the LSB of a frame byte count stored in the 10x19-bit FIFO array as shown in

Figure 6–22.

Figure 6–22. Read Register 6

6.3.6

Read Register 7

When the SCC is programmed for SDLC operation and bit D2 of WR15 is set to ‘1’, RR7

contains the MSB of a frame byte count stored in the 10x19-bit FIFO array, and provides

FIFO status via bits D7 and D6 as shown in Figure 6–23. Bit D7 is set to ‘1’ when the

10x19-bit FIFO overflows; otherwise it is set to ‘0’. Bit D6 is used to determine if status

data will be from the FIFO or directly from the 8-bit Status FIFO (RR1). This bit is set to

‘1’ whenever the 10x19-bit FIFO is not empty; otherwise it is ‘0’.

D7 D6 D5 D4 D3 D2 D1 D0

FIFO Data Available Status

1 = Status Reads Come From 10 x 9 Bit FIFO

0 = Status Reads Come From SCC

MSB Byte Count

FIFO Overflow Status

1 = FIFO Overflowed During Operation

0 = Normal

Figure 6–23. Read Register 7

AM8530 Datasheet(PDF) 146 Page - Advanced Micro Devices