AM8530 datasheet(144/194 Pages) AMD

144 / 194 page

AMD

6–34

have been read out by a DMA controller independently from the CPU but the CRC status

is still available in the Frame Status FIFO.

Bit 5: Receiver Overrun Error

This bit indicates that the receive FIFO has overflowed. Only the character that has been

written over is flagged with this error, and when the character is read, the Error condition

is latched until reset by the Error Reset command. The overrun character and all subse-

quent characters received until the Error Reset command is issued causes a Special Re-

ceive Condition vector to be returned.

Bit 4: Parity Error

When parity is enabled, this bit is set for the characters whose parity does not match the

programmed sense (even/odd). This bit is latched so that once an error occurs, it remains

set until the Error Reset command is issued. If the parity in Special Condition bit is set, a

parity error causes a Special Receive Condition vector to be returned on the character

containing the error and on all subsequent characters until the Error Reset command is

issued.

Bits 3, 2, and 1: Residue Codes 2, 1, And 0

In those cases in SDLC mode where the received I-Field is not an integral multiple of the

character length, these three bits indicate the length of the I-Field and are meaningful

only for the transfer in which the end of frame bit is set. This field is set to “011” by a

channel or hardware reset and is forced to this state in Asynchronous mode. These three

bits can leave this state only if SDLC is selected and a character is received. The codes

signify the following (reference Table 6–9) when a receive character length is eight bits

per character.

I-Field bits are right–justified in all cases. If a receive character length other than eight bits

is used for the I-Field, a table similar to Table 6–9 can be constructed for each different

character length. Table 6–10 shows the residue codes for no residue (the I-Field bound-

ary lies on a character boundary).

Table 6–9. I-Field Bit Selection (8 Bits Only)

I-Field

Residue

Bits in

Last Byte

Previous Byte

100

010

110

001

101

011

111

000

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