AM8530 datasheet(143/194 Pages) AMD

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6–33

the Low-to-High transition on ZC. The interrupt service routing should check the other

External/Status conditions for changes. If none changed, ZC was the source. In polled

applications, check the IP bit in RR3A for a status change and then proceed as in the in-

terrupt service routine.

Bit 0: RX Character Available

This bit is set to ‘1’ when at least one character is available in the receive FIFO and is

reset when the receive FIFO is completely empty. A channel or hardware reset empties

the receive FIFO.

6.3.2

Read Register 1

RR1 contains the Special Receive Condition status bits and the residue codes for the I-

Field in SDLC mode. Figure 6–19 shows the bit positions for RR1.

D7 D6 D5 D4 D3 D2 D1 D0

Residue Code 0

Parity Error

Rx Overrun Error

CRC/Framing Error

All Sent

Residue Code 2

Residue Code 1

End of Frame (SDLC)

* Modified in B Channel.

Figure 6–19. Read Register 1

Bit 7: End of Frame (SDLC)

This bit is used only in SDLC mode and indicates that a valid closing flag has been re-

ceived and that the CRC Error bit and residue codes are valid. This bit can be reset by

issuing the Error Reset command. It is also updated by the first character of the following

frame. This bit is reset in any mode other than SDLC.

Bit 6: CRC/Framing Error

If a framing error occurs (in Asynchronous mode), this bit is set (and not latched) for the

receive character in which the framing error occurred. Detection of a framing error adds

an additional one-half bit to the character time so that the framing error is not interpreted

as a new Start bit. In Synchronous and SDLC modes, this bit indicates the result of com-

paring the CRC checker to the appropriate check value. This bit is reset by issuing an

Error Reset command, but the bit is never latched. Therefore, it is always updated when

the next character is received. When used for CRC error status in Synchronous or SDLC

modes, this bit is usually set since most bit combinations, except for a correctly com-

pleted message, result in a non-zero CRC.

The CRC bit is valid only if CRC is enabled and if the second byte of the CRC is at the

top of the receive data FIFO. IF the Frame Status FIFO is enabled and contains at least

one frame of data, then the CRC bit of the Frame Status FIFO (note that this register is

physically different from the standard RR1) will be valid. Note that the CRC bytes could

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