AM8530 datasheet(139/194 Pages) AMD

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AMD

6–29

RxD input. Transmitted data are never seen inside or outside the SCC in this mode, and

CTS is ignored as a transmit enable. This bit is reset by a channel or hardware reset.

Bit 2: DTR/Transmit DMA Request Function

This bit selects the function of the

DTR/REQ pin. If this bit is set to ‘0’, the DTR/REQ pin

follows the inverted state of the DTR bit in WR5. If this bit is set to ‘1’, the

DTR/REQ pin

goes Low whenever the transmit buffer becomes empty and in any of the synchronous

modes when CRC has been sent at the end of a message. The request function on the

DTR/REQ pin differs from the transmit request function available on the W/REQ pin in

that Request does not go inactive until the internal operation satisfying the request is

complete, which occurs four to five PCLK cycles after the rising edge of READ or WRITE.

If the DMA used is edge-triggered, this difference is unimportant. This bit is reset by a

channel or hardware reset.

Bit 1: Baud Rate Generator Source

This bit selects the source of the clock for the baud rate generator. If this bit is set to ‘0’,

the baud rate generator clock comes from either the

RTxC pin or the XTAL oscillator (de-

pending on the state of the XTAL/no XTAL bit). If this bit is set to ‘1’, the clock for the

baud rate generator is the SCC’s PCLK input. Hardware reset sets this bit to ‘0’, select-

ing the

RTxC pin as the clock source for the baud rate generator.

Bit 0: Baud Rate Generator Enable

This bit controls the operation of the baud rate generator. The counter in the baud rate

generator is enabled for counting when this bit is set to ‘1’, and counting is inhibited when

this bit is set to ‘0’. When this bit is set to ‘1’, change in the state of this bit is not reflected

by the output of the baud rate generator for two counts of the counter. This allows the

command to be synchronized. However, when set to ‘0’, disabling is immediate. This bit is

reset by a hardware reset.

6.2.16

Write Register 15 (External/Status Interrupt

Control)

WR15 is the External/Status source control register. If the External/Status interrupts are

enabled as a group via WR1, bits in this register control which External/Status conditions

can cause an interrupt. Only the External/Status conditions that occur after the controlling

bit is sent to ‘1’, will cause an interrupt. This is true even if an External/Status condition is

pending at the time the bit is set. Bit positions for WR15 are shown in Figure 6–17.

D7 D6 D5 D4 D3 D2 D1 D0

DCD IE

SYNC/HUNT IE

CTS IE

Tx Underrun/EOM IE

SDLC/HDLC Enhancement Enable

Zero Count IE

10 x 19-Bit Frame Status FIFO Enable

Break/Abort IE

Figure 6–17. Write Register 15

AM8530 Datasheet(PDF) 139 Page - Advanced Micro Devices

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