AM8530 datasheet(141/194 Pages) AMD

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6–31

D7 D6 D5 D4 D3 D2 D1 D0

DCD

SYNC/HUNT

CTS

Tx Underrun/EOM

Rx Character Available

Zero Count

Tx Buffer Empty

Break/Abort

Figure 6–18. Read Register 0

Bit 7: Break/Abort

In the Asynchronous mode, this bit is set when a Break sequence (null character plus

framing error) is detected in the receive data stream. This bit is reset when the sequence

is terminated, leaving a single null character in the receive FIFO. This character should

be read and discarded. In SDLC mode, this bit is set by the detection of an Abort se-

quence (seven or more ‘1’s), then reset automatically at the termination of the Abort se-

quence. In either case, if the Break/Abort IE bit is set, an External/Status interrupt is

initiated. Unlike the remainder of the External/Status bits, both transitions are guaranteed

to cause an External/Status interrupt, even if another External/Status interrupt is pending

at the time these transitions occur. This procedure is necessary because Abort or Break

conditions may not persist.

Bit 6: TX Underrun/EOM

This bit is set by a channel or hardware reset and when the transmitter is disabled or a

Send Abort command is issued. This bit can be reset only by the reset Tx Underrun/EOM

Latch command in WR0. When the Transmit Underrun occurs, this bit is set and causes

an External/Status interrupt (if the Tx Underrun/EOM IE bit is set).

Only the 0-to-1 transition of this bit causes an interrupt. This bit is always ‘1’ in Asynchro-

nous mode, unless a reset Tx Underrun/EOM Latch command has been erroneously is-

sued. In this case, the Send Abort command can be issued to set the bit to ‘1’ and at the

same time cause an External/Status interrupt.

Bit 5: Clear to Send

If the CTS IE bit in WR15 is set, this bit indicates the state of the

CTS pin the last time

any of the enabled External/Status bits changed. Any transition on the

CTS pin while no

other interrupt is pending latches the state of the

CTS pin and generates an External/

Status interrupt. Any odd number of transitions on the

CTS pin while another External/

Status interrupt is pending also causes an External/Status interrupt condition. If the CTS

IE bit is reset, it merely reports the current unlatched state of the

CTS pin (i.e., if CTS pin

is Low, this bit will be High).

Bit 4: SYNC/Hunt

The operation of this bit is similar to that of the

CTS bit, except that the condition moni-

tored by the bit varies depending on the mode in which the SCC is operating.

When the XTAL oscillator option is selected in asynchronous modes, this bit is forced to

‘0’ (no External/Status interrupt is generated). Selecting the XTAL oscillator in synchro-

nous or SDLC modes has no effect on the operation of this bit.

AM8530 Datasheet(PDF) 141 Page - Advanced Micro Devices

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