AMD-K6 datasheet(26/346 Pages) AMD

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Internal Architecture

Chapter 2

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Enhanced RISC86®

Microarchitecture

Th e En hanced RISC86 m i croarchitecture defi nes the

characteristics of the AMD-K6. The innovative RISC86

microarchitecture approach implements the x86 instruction set

by internally translating x86 instructions into RISC86

operations. These RISC86 operations were specially designed to

include direct support for the x86 instruction set while

observing the RISC performance principles of fixed length

encoding, regularized instruction fields, and a large register

set. The Enhanced RISC86 microarchitecture used in the

AMD-K6 enables higher processor core performance and

promotes straightforward extensibility in future designs.

Instead of directly executing complex x86 instructions, which

have lengths of 1 to 15 bytes, the AMD-K6 processor executes

the simpler and easier fixed-length RISC86 opcodes, while

maintaining the instruction coding efficiencies found in x86

programs.

Th e AM D-K6 process o r contain s p a ra ll e l decoders , a

centralized RISC86 operation scheduler, and seven execution

units that support superscalar operation—multiple decode,

execution, and retirement—of x86 instructions. These elements

are packed into an aggressive and highly efficient six-stage

pipeline.

Decoders. Decoding of the x86 instructions begins when the

on-chip instruction cache is filled. Predecode logic determines

the length of an x86 instruction on a byte-by-byte basis. This

pre d ec o d e info r m a t io n i s st ored, al ong wit h t h e x 8 6

instructions, in the instruction cache, to be used later by the

decoders. The decoders translate on-the-fly, with no additional

latency, up to two x86 instructions per clock into RISC86

operations.

Note: In this chapter, “clock” refers to a processor clock.

The AMD-K6 processor categorizes x86 instructions into three

types of decodes—short, long and vector. The decoders process

either two short, one long, or one vector decode at a time. The

three types of decodes have the following characteristics:

Short decodes—x86 instructions less than or equal to seven

bytes in length

Long decodes—x86 instructions less than or equal to 11

bytes in length

Vector decodes—complex x86 instructions

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