AMD-K6 datasheet(68/346 Pages) AMD

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Software Environment

Chapter 3

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

The second and third columns list all applicable opcode bytes.

The fourth column lists the modR/M byte when used by the

instruction. The modR/M byte defines the instruction as a

as mm (memory form), mm can only be 10b, 01b or 00b.

The fifth column lists the type of instruction decode — short,

long, and vector. The AMD-K6 decode logic can process two

short, one long, or one vector decode per clock.

The sixth column lists the type of RISC86 operation(s) required

for the instruction. The operation types and corresponding

execution units are as follows:

load, fload, mload—load unit

store, fstore, mstore—store unit

alu—either of the integer execution units

alux—integer X execution unit only

branch—branch condition unit

float—floating-point execution unit

meu—multimedia execution unit for MMX software

limm—load immediate, instruction control unit

Table 10. Integer Instructions

Instruction Mnemonic

First

Byte

Second

Byte

ModR/M

Byte

Decode

Type

RISC86®

Opcodes

AAA

37h

vector

AAD

D5h

0Ah

vector

AAM

D4h

0Ah

vector

AAS

3Fh

vector

ADC mreg8, reg8

10h

11-xxx-xxx

short

alux

ADC mem8, reg8

10h

mm-xxx-xxx

long

load, alux, store

ADC mreg16/32, reg16/32

11h

11-xxx-xxx

short

alu

ADC mem16/32, reg16/32

11h

mm-xxx-xxx

long

load, alu, store

ADC reg8, mreg8

12h

11-xxx-xxx

short

alux

ADC reg8, mem8

12h

mm-xxx-xxx

short

load, alux

ADC reg16/32, mreg16/32

13h

11-xxx-xxx

short

alu

ADC reg16/32, mem16/32

13h

mm-xxx-xxx

short

load, alu

ADC AL, imm8

14h

xx-xxx-xxx

short

alux

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