AMD-K6 datasheet(55/346 Pages) AMD

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Chapter 3

Software Environment

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Model-Specific

Registers (MSR)

The AMD-K6 processor provides five MSRs. The value in the

ECX register selects the MSR to be addressed by the RDMSR

and WRMSR instructions. The values in EAX and EDX are used

as inputs and outputs by the RDMSR and WRMSR instructions.

Table 5 lists the MSRs and the corresponding value of the ECX

Fo r mo re in fo rma tio n ab o ut the RD MSR and WRMSR

instructions, see the AMD K86™ Family BIOS and Software Tools

Development Guide, order# 21062.

MCAR and MCTR. The AMD-K6 processor does not support the

generation of a machine check exception. However, the

processor does provide a 64-bit Machine Check Address

(MCTR), and a Machine Check Enable (MCE) bit in CR4.

Because the processor does not support machine check

exceptions, the contents of the MCAR and MCTR are only

affected by the WRMSR instruction and by RESET being

sampled asserted (where all bits in each register are reset to 0).

Figure 28. Machine-Check Address Register (MCAR)

Table 5.

Model-Specific Registers (MSRs)

Model-Specific Register

Value of ECX

Machine Check Address Register (MCAR)

00h

Machine Check Type Register (MCTR)

01h

Test Register 12 (TR12)

0Eh

Time Stamp Counter (TSC)

10h

Write Handling Control Register (WHCR)

C000_0082h

MCAR

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