AMD-K6 datasheet(27/346 Pages) AMD

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Chapter 2

Internal Architecture

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Short and long decodes are processed completely within the

decoders. Vector decodes are started by the decoders and then

completed by fetched sequences from an on-chip ROM. After

decoding, the RISC86 operations are delivered to the scheduler

for dispatching to the executions units.

Scheduler/Instruction Control Unit. The centraliz ed scheduler or

buffer is managed by the Instruction Control Unit (ICU). The

ICU buffers and manages up to 24 RISC86 operations at a time.

This equals from 6 to 12 x86 instructions. This buffer size (24) is

perfectly matched to the processor’s six-stage RISC86 pipeline

and seven parallel execution units. The scheduler accepts as

many as four RISC86 operations at a time from the decoders.

The ICU is capable of simultaneously issuing up to six RISC86

operations at a time to the execution units. This consists of the

following types of operations:

Memory load operation

Memory store operation

Complex integer or MMX register operation

Simple integer register operation

Floating-point register operation

Branch condition evaluation

Registers. The scheduler uses 48 physical registers that are

contained within the RISC86 microarchitecture when managing

the 24 RISC86 operations. The 48 physical registers are located

in a general register file and are grouped as 24 general

registers, plus 24 renaming registers. The 24 general registers

consist of 16 scratch registers and eight registers that

correspond to the x86 general purpose registers — EAX, EBX,

ECX, EDX, EBP, ESP, ESI and EDI.

Branch Logic. The AMD-K6 processor is designed with highly

sophisticated dynamic branch logic consisting of the following:

Branch history/Prediction table

Branch target cache

Return address stack

The AMD-K6 implements a two-level branch prediction scheme

based on an 8192-entry branch history table. The branch history

table stores prediction information that is used for predicting

conditional branches. Because the branch history table does not

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