AMD-K6 datasheet(28/346 Pages) AMD

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Internal Architecture

Chapter 2

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

store predicted target addresses, special address ALUs

calculate target addresses on-the-fly during instruction decode.

Th e bra n ch t a rg e t c a ch e aug m e n t s predic t e d branch

performance by avoiding a one clock cache-fetch penalty. This

specialized target cache does this by supplying the first 16 bytes

of target instructions to the decoders when branches are

predicted. The return address stack is a unique device

specifically designed for optimizing CALL and RETURN pairs.

In summary, the AMD-K6 uses dynamic branch logic to

minimize delays due to the branch instructions that are

common in x86 software.

AMD-K6® Processor Block Diagram. As shown in Figure 1 on page 11,

the high-performance, out-of-order execution engine of the

AMD-K6 processor is mated to a split level-one 64-Kbyte

writeback cache with 32 Kbytes of instruction cache and 32

Kbytes of data cache. The instruction cache feeds the decoders

and, in turn, the decoders feed the scheduler. The ICU issues

and retires RISC86 operations contained in the scheduler. The

system bus interface is an industry-standard 64-bit Pentium®

processor demultiplexed bus.

The AMD-K6 processor combines the latest in processor

microarchitecture to provide the highest x86 performance for

to d ay ’s pers o n al computers . Th e AMD-K6 o ffers tr ue

sixth-generation performance and full x86 binary software

compatibility.

AMD-K6 Datasheet(PDF) 28 Page - Advanced Micro Devices