AMD-K6 datasheet(29/346 Pages) AMD

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Chapter 2

Internal Architecture

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Figure 1. AMD-K6® Processor Block Diagram

2.3

Cache, Instruction Prefetch, and Predecode Bits

The writeback level-one cache on the AMD-K6 processor is

organized as a separate 32-Kbyte instruction cache and a

32-Kbyte data cache with two-way set associativity. The cache

line size is 32 bytes and lines are prefetched from main memory

using an effi cient pipelined burst tran saction. As the

instruction cache is filled, each instruction byte is analyzed for

instruction boundaries using predecoding logic. Predecoding

annotates each instruction byte with information that later

enables the decoders to efficiently decode multiple instructions

simultaneously.

Cache

The processor cache design takes advantage of a sectored

organization (see Figure 2 on page 12). Each sector consists of

64 bytes configured as two 32-byte cache lines. The two cache

lines of a sector share a common tag but have separate pairs of

MESI (Modified, Exclusive, Shared, Invalid) bits that track the

state of each cache line.

Integer X

(Register) Unit

Store

Unit

Integer Y

(Register) Unit

Floating-Point

Unit

Branch

(Resolving) Unit

Store

Queue

Instruction

Control Unit

Scheduler

Buffer

(24 RISC86)

Six RISC86®

Operation Issue

Out-of-Order

Execution Engine

Level-One Dual-Port Data Cache (32 KByte)

128-Entry DTLB

Level-One Instruction Cache

(32 KByte + Predecode)

64-Entry ITLB

Dual Instruction Decoders

x86 to RISC86

Branch Logic

(8192-Entry BHT)

(16-Entry BTC)

(16-Entry RAS)

Load

Unit

Multimedia

Unit

Predecode

Logic

Level-One Cache

Controller

Socket 7

Bus

Interface

16-Byte Fetch

Four RISC86

Decode

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