AMD-K6 datasheet(33/346 Pages) AMD

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Chapter 2

Internal Architecture

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

The AMD-K6 processor uses a combination of decoders to

convert x86 instructions into RISC86 operations. The hardware

consists of three sets of decoders—two parallel short decoders,

one long decoder, and one vectoring decoder. The parallel short

decoders translate the most commonly-used x86 instructions

( moves, shifts, branches, ALU, MMX, FPU) into zero, one, or

two RISC86 operations each. The short decoders only operate

on x86 instructions that are up to seven bytes long. In addition,

they are designed to decode up to two x86 instructions per

clock. The commonly-used x86 instructions that are greater

than seven bytes but not m ore than 11 bytes long, and

semi-commonly-used x86 instructions that are up to seven bytes

long are handled by the long decoder.

The long decoder only performs one decode per clock and

generates up to four RISC86 operations. All other translations

(complex instructions, serializing conditions, interrupts and

exceptions, etc.) are handled by a combination of the vector

decoder and RISC86 operation sequences fetched from an

on-chip ROM. For complex operations, the vector decoder logic

provides the first set of RISC86 operations and a vector (initial

ROM address) to a sequence of further RISC86 operations. The

same types of RISC86 operations are fetched from the ROM as

those that are generated by the hardware decoders.

Note: Although all three sets of decoders are simultaneously fed a

copy of the instruction buffer contents, only one of the three

types of decoders is used during any one decode clock.

The decoders or the RISC86 sequencer always generate a group

of four RISC86 operations. For decodes that cannot fill the entire

group with four RISC86 operations, RISC86 NOP operations are

placed in the empty locations of the grouping. For example, a

long-decoded x86 instruction that converts to only three RISC86

operations is padded with a single RISC86 NOP operation and

then passed to the scheduler. Up to six groups or 24 RISC86

operations can be placed in the scheduler at a time.

All of the common, and a few of the uncommon, floating-point

instructions (also known as ESC instructions) are hardware

decoded as short decodes. This decode generates a RISC86

floating-point operation and, optionally, an associated

floating-point load or store operation. Floating-point or ESC

instruction decode is only allowed in the first short decoder, but

non-ESC instructions, excluding MMX instructions, can be

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