AMD-K6 datasheet(63/346 Pages) AMD

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Chapter 3

Software Environment

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Figure 39. Page Table Entry (PTE)

Descriptors and Gates

There are various types of structures and registers in the x86

architecture that define, protect, and isolate code segments,

data segments, task state segments, and gates. These structures

are called descriptors.

Figure 40 on page 46 shows the application segment descriptor

format. Table 7 contains information describing the memory

segment type to which the descriptor points. The application

segment descriptor is used to point to either a data or code

segment.

Figure 41 on page 47 shows the system segment descriptor

format. Table 8 contains information describing the type of

segment or gate to which the descriptor points. The system

segment descriptor is used to point to a task state segment, a

call gate, or a local descriptor table.

The AMD-K6 processor uses gates to transfer control between

executable segments with different privilege levels. Figure 42

on page 48 shows the format of the gate descriptor types. Table

8 contains information describing the type of segment or gate

to which the descriptor points.

6543

210

Physical Page Base Address

Symbol

Description

Bits

AVL

Available to Software

11–9

Reserved

8–7

Dirty

Accessed

PCD

Page Cache Disable

PWT

Page Writethrough

U/S

User/Supervisor

W/R

Write/Read

Present (valid)

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